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Z8F021ASH020SC 数据表(PDF) 247 Page - Zilog, Inc. |
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Z8F021ASH020SC 数据表(HTML) 247 Page - Zilog, Inc. |
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247 / 276 page ![]() PS022815-0206 Electrical Characteristics Z8 Encore! XP® 4K Series Product Specification 228 UART Timing Figure 37 and Table 145 provide timing information for UART pins for the case where CTS is used for flow control. The CTS to DE assertion delay (T1) assumes the transmit data register has been loaded with data prior to CTS assertion. Figure 37. UART Timing With CTS Table 145. UART Timing With CTS Parameter Abbreviation Delay (ns) Minimum Maximum UART T1 CTS Fall to DE output delay 2 * XIN period 2 * XIN period + 1 bit time T2 DE assertion to TXD falling edge (start bit) delay ± 5 T3 End of Stop Bit(s) to DE deassertion delay ± 5 CTS DE T1 (Output) TXD T2 (Output) (Input) start bit 0 bit 1 bit 7 parity stop end of stop bit(s) T3 |
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