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Z8F021ASH020SC 数据表(PDF) 248 Page - Zilog, Inc. |
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Z8F021ASH020SC 数据表(HTML) 248 Page - Zilog, Inc. |
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248 / 276 page ![]() PS022815-0206 Electrical Characteristics Z8 Encore! XP® 4K Series Product Specification 229 Figure 38 and Table 146 provide timing information for UART pins for the case where CTS is not used for flow control. DE asserts after the transmit data register has been writ- ten. DE remains asserted for multiple characters as long as the transmit data register is written with the next character before the current character has completed. Figure 38. UART Timing Without CTS Table 146. UART Timing Without CTS Parameter Abbreviation Delay (ns) Minimum Maximum UART T1 DE assertion to TXD falling edge (start bit) delay 1 * XIN period 1 bit time T2 End of Stop Bit(s) to DE deassertion delay (Tx data register is empty) ± 5 DE T1 (Output) TXD T2 (Output) start bit0 bit 1 bit 7 parity stop end of stop bit(s) |
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