LSM6DST datasheet(120/180 Pages) STMICROELECTRONICS

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SPI2 register description

LSM6DST

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DocID033525 Rev 2

11.10

SPI2_INT_OIS (6Fh)

OIS interrupt configuration register and accelerometer self-test enable setting. The auxiliary

SPI interface can write this register when the OIS_CTRL_FROM_UI bit in the

FUNC_CFG_ACCESS (01h) register is equal to 0 (SPI2 Full control mode); this register is

read-only when the OIS_CTRL_FROM_UI bit is equal to 1 (Primary IF Full control mode)

and shows the content of the UI_INT_OIS (6Fh) register.

Table 218. SPI_INT_OIS register description

Table 217. SPI_INT_OIS register

INT2_

DRDY_

OIS

LVL2_OIS

DEN_LH_

OIS

0(1)

1. This bit must be set to '0' for the correct operation of the device.

ST1_XL_

OIS

ST0_XL_

OIS

INT2_DRDY_

OIS

Enables OIS chain DRDY on INT2 pin. This setting has priority over all other INT2

settings.

LVL2_OIS

Enables level-sensitive latched mode on the OIS chain. Default value: 0

DEN_LH_

OIS

Indicates polarity of DEN signal on OIS chain

(0: DEN pin is active-low;

1: DEN pin is active-high)

ST[1:0]_XL_

OIS

Selects accelerometer self-test – effective only if XL OIS chain is enabled. Default

value: 00

(00: Normal mode;

01: Positive sign self-test;

10: Negative sign self-test;

11: not allowed)

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