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VVMU_WARN_FALL (min)

VVMU_WARN_FALL (max)

VVMU_WARN_RISE (max)

VVMU_WARN_RISE (min)

VVM

FETs ON

Time

FETs OFF

tRETRY

FETs ON

tRETRY

Figure 8-24. VM Under Voltage Warning

8.3.11.2.2 VM Under Voltage Warn Report Only (VMUV_WARN_MODE = 10b)

No protective action occurs after a VM under voltage warn event in this mode. The VM under voltage warn

event is reported by driving the nFAULT pin low and setting the FAULT, UVW bits (in DEV_STS register) and

VMUV_WARN bit (in SUP_STS register) to 1b. DRV8317 continues to operate as usual. The external controller

manages the VM under voltage warn condition by acting appropriately. The reporting clears (nFAULT pin is

released, FAULT, UVW and VMUV_WARN bits are set to 0b) when a clear fault command is issued either

through the FLT_CLR bit or an nSLEEP reset pulse (tRST).

8.3.11.2.3 VM Under Voltage Warn Disabled (VMUV_WARN_MODE = 11b)

No action is taken and no reporting (nFAULT pin, status register bits) is done after a VM under voltage warn

event in this mode.

8.3.11.3 Over Current Protection (OCP)

A MOSFET over current event is sensed by monitoring the current flowing through each of the FETs. If the

current through a FET exceeds the OCP threshold (IOCP) for longer than the OCP deglitch time (tOCP), an OCP

event is recognized and action is taken according to OCP_MODE. In order to avoid false trigger of OCP at PWM

transitions, due to ringing in the phase voltage, there is a blanking time (tBLANK) applied after each PWM edge.

During blanking time, OCP events are ignored.

In DRV8317H, the tOCP is fixed at 0.6-µs (typical), tBLANK is fixed at 0.7-µs (typical) and the OCP_MODE is set

to 001b with retry time of 5-ms. In DRV8317S, the tOCP is configured by OCP_DEG, the tBLANK is configured by

OCP_TBLANK and the OCP_MODE can be configured in four different modes: OCP latched shutdown, OCP

automatic retry with fast and slow retry times and OCP report only.

Note

(tOCP + tBLANK) should not exceed 2-µs

8.3.11.3.1 OCP Latched Fault (OCP_MODE = 010b)

After an OCP event in this mode, all MOSFETs are in Hi-Z and the nFAULT pin is driven low. The FAULT, OCP

bits (in DEV_STS register) and corresponding FETs' OCP bits (in DRV_STS register) are set to 1b. Normal

operation resumes (pre-driver operation, FAULT, OCP, corresponding FETs' OCP bits set to 0b and the nFAULT

pin is released) when a clear fault command is issued either through the FLT_CLR bit or an nSLEEP reset pulse

(tRST).

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DRV8317

SLVSGT3 – DECEMBER 2022

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