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DRV8317 数据表(PDF) 40 Page - Texas Instruments |
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DRV8317 数据表(HTML) 40 Page - Texas Instruments |
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40 / 69 page ![]() 8.6.3 OT_STS Register (Offset = 4h) [Reset = 0000h] OT_STS is shown in Figure 8-30 and described in Table 8-13. Return to the Table 8-9. Figure 8-30. OT_STS Register 15 14 13 12 11 10 9 8 PARITY RESERVED R-0h R-0-0h 7 6 5 4 3 2 1 0 RESERVED RESERVED OTW_FET OTS_FET R-0-0h R-0h R-0h R-0h Table 8-13. OT_STS Register Field Descriptions Bit Field Type Reset Description 15 PARITY R 0h Parity Bit if SPI_PEN is set to '1' otherwise reserved 14-3 RESERVED R-0 0h Reserved 2 RESERVED R 0h Reserved 1 OTW_FET R 0h FET over temperature warning fault status. Auto cleared if retry is enabled in OTF_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP. 0h = No FET over temperature warning is detected 1h = FET over temperature warning is detected 0 OTS_FET R 0h FET over temperature shutdown fault status. Auto cleared if retry is enabled in OTF_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP. 0h = No FET over temperature shutdown is detected 1h = FET over temperature shutdown is detected DRV8317 SLVSGT3 – DECEMBER 2022 www.ti.com 40 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8317 |
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