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DRV8317 数据表(PDF) 51 Page - Texas Instruments |
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DRV8317 数据表(HTML) 51 Page - Texas Instruments |
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51 / 69 page  8.6.13 PWM_CTRL Register (Offset = 20h) [Reset = 0000h] PWM_CTRL is shown in Figure 8-40 and described in Table 8-23. Return to the Table 8-9. Figure 8-40. PWM_CTRL Register 15 14 13 12 11 10 9 8 PARITY RESERVED R/W-0h R-0-0h 7 6 5 4 3 2 1 0 RESERVED SSC_DIS PWM_MODE R-0-0h R/W-0h R/W-0h Table 8-23. PWM_CTRL Register Field Descriptions Bit Field Type Reset Description 15 PARITY R/W 0h Parity Bit if SPI_PEN is set to '1' otherwise reserved 14-3 RESERVED R-0 0h Reserved 2 SSC_DIS R/W 0h Disable SSC on oscillator 0h = SSC enabled 1h = SSC disabled 1-0 PWM_MODE R/W 0h PWM mode selection 0h = 6x mode 1h = 6x direct mode 2h = 3x mode 3h = 3x direct mode www.ti.com DRV8317 SLVSGT3 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: DRV8317 |
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