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DRV8317 数据表(PDF) 43 Page - Texas Instruments |
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DRV8317 数据表(HTML) 43 Page - Texas Instruments |
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43 / 69 page  8.6.6 SYSIF_STS Register (Offset = 7h) [Reset = 0000h] SYSIF_STS is shown in Figure 8-33 and described in Table 8-16. Return to the Table 8-9. Figure 8-33. SYSIF_STS Register 15 14 13 12 11 10 9 8 PARITY RESERVED R-0h R-0-0h 7 6 5 4 3 2 1 0 RESERVED OTPLD_ERR RESERVED SPI_PARITY BUS_CNT FRM_ERR R-0-0h R-0h R-0-0h R-0h R-0h R-0h Table 8-16. SYSIF_STS Register Field Descriptions Bit Field Type Reset Description 15 PARITY R 0h Parity Bit if SPI_PEN is set to '1' otherwise reserved 14-5 RESERVED R-0 0h Reserved 4 OTPLD_ERR R 0h OTP parity error during load 0h = No OTP read error is detected 1h = OTP read error is detected 3 RESERVED R-0 0h Reserved 2 SPI_PARITY R 0h SPI parity error 0h = No SPI Parity Error is detected 1h = SPI Parity Error is detected 1 BUS_CNT R 0h SPI bus contention error 0h = No SPI Bus Contention Error is detected 1h = SPI Bus Contention Error is detected 0 FRM_ERR R 0h SPI frame error 0h = No SPI Frame Error is detected 1h = SPI Frame Error is detected www.ti.com DRV8317 SLVSGT3 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: DRV8317 |
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