DRV8317 datasheet(20/69 Pages) TI

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8.3.2.2 3x PWM Mode

In 3x PWM mode, the INHx pin controls each half-bridge and supports two output states: low or high. To

configure DRV8317H in 3x PWM mode, connect the MODE pin to AVDD or keep the MODE pin floating (Hi-Z).

To enable 3x PWM mode in DRV8317S, set PWM_MODE to 10b or 11b. The INLx pin is used to put the half

bridge in the Hi-Z state. If the Hi-Z state is not required, tie all INLx pins to logic high (for example, by tying them

to AVDD). The corresponding INHx and INLx signals control the output state as listed in Table 8-4.

Table 8-4. 3x PWM Mode Truth Table

INLx

INHx

OUTx

Hi-Z

Figure 8-4 shows the typical application diagram of the DRV8317 configured in 3x PWM mode.

Logic

Gate

Drive

and

OCP

INHC

INLA

nSLEEP

INHA

INHB

OUTB

OUTA

OUTC

BLDC

Motor

INLB

INLC

Controller

AVDD

PGND

Figure 8-4. 3x PWM Mode

8.3.3 Device Interface Modes

The DRV8317 family of devices supports two different interface modes (SPI and hardware) to offer either

increased simplicity (hardware interface) or greater flexibility (SPI interface). The SPI (DRV8317S) and hardware

(DRV8317H) interface modes share the same four pins, allowing the different versions to be pin-to-pin

compatible. Designers are encouraged to evaluate with the SPI interface version due to ease of changing

settings, and may consider switching to the hardware interface with minimal modifications to the design.

DRV8317

SLVSGT3 – DECEMBER 2022

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