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DRV8317 数据表(PDF) 18 Page - Texas Instruments |
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DRV8317 数据表(HTML) 18 Page - Texas Instruments |
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18 / 69 page  8.3 Feature Description Table 8-1 lists the recommended values of the external components for the driver. Table 8-1. DRV8317 External Components COMPONENTS PIN 1 PIN 2 RECOMMENDED CVM1 VM PGND X5R or X7R, 0.1-µF, (2 x VM)-rated capacitor CVM2 VM PGND ≥ 10-µF, (2 x VM)-rated electrolytic capacitor CVIN_AVDD1 VIN_AVDD AGND X5R or X7R, 0.1-µF, (2 x VIN_AVDD)-rated capacitor CVIN_AVDD2 VIN_AVDD AGND ≥ 10-µF, (2 x VIN_AVDD)-rated capacitor CFLY CPH CPL X5R or X7R, 0.1-µF, (2 x VM)-rated capacitor CCP CP VM X5R or X7R, 16-V, 1-µF capacitor CAVDD AVDD AGND X5R or X7R, 2.2-µF (no external load) 4.7-µF (up to 80mA load), 6.3-V capacitor RnFAULT AVDD nFAULT 5.1-kΩ, Pull-up resistor RMODE MODE AGND Section 8.3.3.2 RSLEW SLEW AGND Section 8.3.3.2 RGAIN GAIN AGND Section 8.3.3.2 CCSAREF CSAREF AGND X5R or X7R, 0.1-µF, (2 x CSAREF)-rated capacitor 8.3.1 Output Stage The DRV8317 consists of integrated N-channel FETs (high-side and low-side) connected in a three-phase bridge configuration. A doubler charge pump provides the proper gate-bias voltage to the high-side N-channel FETs across a wide operating (VM) voltage range in addition to providing 100% duty-cycle support. An internal linear regulator operating from the VM supply provides the gate-bias voltage (VLS) for the low-side N-channel FETs. 8.3.2 Control Modes The DRV8317 family of devices provides three different control modes to support various commutation and control methods. Table 8-2 shows the various modes of the DRV8317 device. Table 8-2. PWM Control Modes PWM Control Mode PWM_MODE register (DRV8317S) MODE Pin (DRV8317H) 6x PWM PWM_MODE = 00b MODE pin tied to AGND directly or tied to AGND via 47-kΩ resistor 6x direct PWM PWM_MODE = 01b Not Available 3x PWM PWM_MODE = 10b MODE pin floating (Hi-Z) or tied to AVDD 3x direct PWM PWM_MODE = 11b Not Available The difference between 6x PWM (or 3x PWM) and 6x direct PWM (or 3x direct PWM) is that in the direct (6x or 3x) PWM mode, the delay compensation logic circuit is bypassed and the inputs at INHx, INLx are directly passed on to the gate driver circuit. In the gate driver circuit, a dead time (tDRV_DEAD) is added before driving the FETs to prevent shoot through faults - this dead time is available in all the four PWM control modes. Note TI does not recommend changing the MODE pin or PWM_MODE register during power up of the device (during tWAKE). The MODE pin setting on DRV8317H is latched at power up, so set nSLEEP = 0 before changing the MODE pin configuration on the DRV8317H. In DRV8317S, set all INHx and INLx pins to logic low before changing the PWM_MODE register. DRV8317 SLVSGT3 – DECEMBER 2022 www.ti.com 18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8317 |
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