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DRV8317 数据表(PDF) 39 Page - Texas Instruments |
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DRV8317 数据表(HTML) 39 Page - Texas Instruments |
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39 / 69 page  8.6.2 DEV_RSTS Register (Offset = 2h) [Reset = 0000h] DEV_RSTS is shown in Figure 8-29 and described in Table 8-12. Return to the Table 8-9. Figure 8-29. DEV_RSTS Register 15 14 13 12 11 10 9 8 RESERVED DNRDY_RSTS SYSF_RSTS R-0-0h R-0h R-0h 7 6 5 4 3 2 1 0 RESERVED SPIF_RSTS OCP_RSTS VMUV_WRSTS OVP_RSTS UVP_RSTS OTF_RSTS RESERVED R-0-0h R-0h R-0h R-0-0h R-0-0h R-0h R-0h R-0-0h Table 8-12. DEV_RSTS Register Field Descriptions Bit Field Type Reset Description 15-10 RESERVED R-0 0h Reserved 9 DNRDY_RSTS R 0h Device not ready indicator 0h = Device not ready to drive PWMs 1h = Device ready to drive PWMs 8 SYSF_RSTS R 0h OTP parity error during load, raw status. Cleared by write to FLT_CLR or reset pulse on nSLEEP 0h = No parity error during OTP load 1h = Parity error occurred during OTP load 7 RESERVED R-0 0h Reserved 6 SPIF_RSTS R 0h SPI fault raw status. Cleared by write to FLT_CLR or reset pulse on nSLEEP 0h = No SPI fault is detected 1h = SPI fault is detected 5 OCP_RSTS R 0h Driver OCP raw status. Auto cleared if retry is enabled in OCP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP. 0h = No over current condition is detected 1h = Over current condition is detected 4 VMUV_WRSTS R-0 0h VM under voltage warning fault raw status. Auto cleared if retry is enabled in VMUV_WARN_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP. 0h = No VM under voltage warn condition is detected (VM > VMUV_WARN_RISE threshold) 1h = VM under voltage warn condition is detected (VM < VMUV_WARN_FALL threshold) 3 OVP_RSTS R-0 0h Over voltage protection fault raw status. Auto cleared if retry is enabled in OVP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP. 0h = No over voltage condition on VM is detected 1h = VM over voltage condition is detected 2 UVP_RSTS R 0h Under voltage protection fault raw status. Auto cleared if retry is enabled in UVP_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP. 0h = No under voltage condition is detected on VM or CP 1h = Under voltage condition is detected on VM or CP 1 OTF_RSTS R 0h Over temperature fault raw status. Auto cleared if retry is enabled in OTF_MODE. Can also be cleared by write to FLT_CLR or reset pulse on nSLEEP. 0h = No over temperature warning/shutdown is detected 1h = Over temperature warning/shutdown is detected 0 RESERVED R-0 0h Reserved www.ti.com DRV8317 SLVSGT3 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: DRV8317 |
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