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DRV8317 数据表(PDF) 52 Page - Texas Instruments |
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DRV8317 数据表(HTML) 52 Page - Texas Instruments |
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52 / 69 page ![]() 8.6.14 DRV_CTRL Register (Offset = 22h) [Reset = 0003h] DRV_CTRL is shown in Figure 8-41 and described in Table 8-24. Return to the Table 8-9. Figure 8-41. DRV_CTRL Register 15 14 13 12 11 10 9 8 PARITY RESERVED DLY_TARGET R/W-0h R-0-0h R/W-0h 7 6 5 4 3 2 1 0 DLYCMP_EN RESERVED SLEW_RATE R/W-0h R-0-0h R/W-3h Table 8-24. DRV_CTRL Register Field Descriptions Bit Field Type Reset Description 15 PARITY R/W 0h Parity Bit if SPI_PEN is set to '1' otherwise reserved 14-12 RESERVED R-0 0h Reserved 11-8 DLY_TARGET R/W 0h Delay Target : DLY_TARGET * 0.2µs 7 DLYCMP_EN R/W 0h Driver Delay Compensation enable 0h = Delay compensation disabled 1h = Delay compensation enabled 6-2 RESERVED R-0 0h Reserved 1-0 SLEW_RATE R/W 3h Slew rate settings 0h = Slew rate is 25 V/µs 1h = Slew rate is 50 V/µs 2h = Slew rate is 125 V/µs 3h = Slew rate is 200 V/µs DRV8317 SLVSGT3 – DECEMBER 2022 www.ti.com 52 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8317 |
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