DRV8317 datasheet(22/69 Pages) TI

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circuits like MCU, logic, hall sensors, LEDs for up to 80 mA. The output of the AVDD regulator should be

bypassed near the AVDD pin with a X5R or X7R, up to 7.05µF (4.7µF typical), 6.3-V ceramic capacitor routed

directly back to the adjacent AGND ground pin.

The AVDD nominal, no-load output voltage is 3.3 V.

AVDD

AGND

CAVDD

External Load

REF

VIN_AVDD

Figure 8-7. AVDD Linear Regulator Block Diagram

Use Equation 1 to calculate the power dissipated in the device by the AVDD linear regulator.

P = (VVIN_AVDD - VAVDD) x IAVDD

(1)

The supply input voltage for AVDD regulator (VIN_AVDD) can be same as VM supply voltage, or lower or higher

than VM supply voltage.

8.3.5 Charge Pump

The DRV8317 requires a gate-drive voltage higher than the VM power supply to enhance the high-side FETs

fully because the output stages uses N-channel FETs for both high-side and low-side. The DRV8317 integrates a

charge pump circuit that generates a voltage above the VM supply for this purpose.

The charge pump requires two external capacitors for operation. See Table 8-1 for details on the capacitor value.

The charge pump shuts down when nSLEEP is low.

CCP

CPH

Charge

Pump

Control

CPL

CFLY

Figure 8-8. DRV8317 Charge Pump

DRV8317

SLVSGT3 – DECEMBER 2022

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