DRV8317 datasheet(5/69 Pages) TI

5 / 69 page

Table 6-1. Pin Functions (continued)

36-pin package

TYPE

(1)

DESCRIPTION

NAME

DRV8317S DRV8317H

CSAREF

PWR I

Current sense amplifier power supply input/reference. Connect a X5R or X7R, 0.1-

µF, 6.3-V ceramic capacitor between the CSAREF and AGND pins.

GAIN

—

Available only in hardware variant (DRV8317H). The pin is a 4-level input pin for

current sense amplifier gain setting.

INHA

High-side driver control input for OUTA. This pin controls the state of the high-side

MOSFET in 6x/3x PWM Mode.

INHB

High-side driver control input for OUTB. This pin controls the state of the high-side

MOSFET in 6x/3x PWM Mode.

INHC

High-side driver control input for OUTC. This pin controls the state of the high-side

MOSFET in 6x/3x PWM Mode.

INLA

Low-side driver control input for OUTA. This pin controls the state of the low-side

MOSFET in 6x PWM Mode.

INLB

Low-side driver control input for OUTB. This pin controls the state of the low-side

MOSFET in 6x PWM Mode.

INLC

Low-side driver control input for OUTC. This pin controls the state of the low-side

MOSFET in 6x PWM Mode.

MODE

—

Available only in hardware variant (DRV8317H). This is a 4-level input pin for PWM

mode setting.

3, 32

—

No connect. Leave the pin floating.

nFAULT

Fault indication pin. Pulled low during fault condition. Open-drain output; requires an

external pull-up resistor to AVDD.

nSCS

—

Available only in SPI variant (DRV8317S). Serial chip select. A logic low on this pin

enables serial interface communication.

nSLEEP

When this pin is logic low the device goes to a low-power sleep mode. A 15 to 50-µs

low pulse on nSLEEP pin can be used to reset fault conditions without entering sleep

mode.

OUTA

11, 12

Half-bridge output A. Connect to motor winding.

OUTB

14, 15

Half-bridge output B. Connect to motor winding.

OUTC

17, 18

Half-bridge output C. Connect to motor winding.

PGND

10, 13, 16,

PWR

Device power ground. Connect to a separate ground plane.

(1)

SCLK

—

Available only in SPI variant (DRV8317S). Serial clock input. Serial data is shifted

out on the rising edge and captured on the falling edge of SCLK.

SDI

—

Available only in SPI variant (DRV8317S). Serial data input. Data (input) is captured

on the falling edge of the SCLK pin (SPI devices).

SDO

—

Available only in SPI variant (DRV8317S). Serial data output. Data (output) is shifted

out on the rising edge of the SCLK pin.

SLEW

—

Available only in hardware variant (DRV8317H). This pin is a 4-level input pin for

OUTx voltage slew rate setting.

SOA

Current sense amplifier output for OUTA.

SOB

Current sense amplifier output for OUTB.

SOC

Current sense amplifier output for OUTC.

VIN_AVDD

PWR

Input supply for AVDD LDO

8, 9, 20

PWR

Device and motor power supply. Connect to motor supply voltage; bypass to PGND

with a 0.1-µF capacitor plus one bulk capacitor. TI recommends a capacitor voltage

rating at least twice the normal operating voltage of the device

Thermal

pad

PWR

Must be connected to AGND.

(1)

I = input, O = output, PWR = power, GND = ground, NC = no connect

www.ti.com

DRV8317

SLVSGT3 – DECEMBER 2022

Submit Document Feedback

Product Folder Links: DRV8317

DRV8317 数据表(PDF) 5 Page - Texas Instruments

DRV8317 数据表(HTML) 5 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

数据表下载

链接网址

DRV8317 数据表(PDF) 5 Page - Texas Instruments

DRV8317 数据表(HTML) 5 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

数据表 下载

链接网址

数据表下载