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DRV8317 数据表(PDF) 47 Page - Texas Instruments |
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DRV8317 数据表(HTML) 47 Page - Texas Instruments |
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47 / 69 page  8.6.9 DRVF_TCTRL Register (Offset = 13h) [Reset = 0155h] DRVF_TCTRL is shown in Figure 8-36 and described in Table 8-19. Return to the Table 8-9. Figure 8-36. DRVF_TCTRL Register 15 14 13 12 11 10 9 8 PARITY RESERVED RESERVED R/W-0h R-0-0h R/W-1h 7 6 5 4 3 2 1 0 RESERVED OCP_DEG OCP_TBLANK VMUV_WARN_TDG R/W-1h R/W-1h R/W-1h R/W-1h Table 8-19. DRVF_TCTRL Register Field Descriptions Bit Field Type Reset Description 15 PARITY R/W 0h Parity Bit if SPI_PEN is set to '1' otherwise reserved 14-10 RESERVED R-0 0h Reserved 9-8 RESERVED R/W 1h Reserved 7-6 RESERVED R/W 1h Reserved 5-4 OCP_DEG R/W 1h OCP deglitch time 0h = 0.3 µs 1h = 0.6 µs 2h = 0.9 µs 3h = 1.2 µs 3-2 OCP_TBLANK R/W 1h OCP blanking time 0h = 0.3 µs 1h = 0.7 µs 2h = 2 µs 3h = 1.2 µs 1-0 VMUV_WARN_TDG R/W 1h VM under voltage warning deglitch time 0h = 0.3 µs 1h = 0.6 µs 2h = 0.9 µs 3h = 2 µs www.ti.com DRV8317 SLVSGT3 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: DRV8317 |
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