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DRV8317 数据表(PDF) 49 Page - Texas Instruments |
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DRV8317 数据表(HTML) 49 Page - Texas Instruments |
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49 / 69 page ![]() 8.6.11 FLT_CLR Register (Offset = 17h) [Reset = 0000h] FLT_CLR is shown in Figure 8-38 and described in Table 8-21. Return to the Table 8-9. Figure 8-38. FLT_CLR Register 15 14 13 12 11 10 9 8 RESERVED RESERVED R/W-0h R-0-0h 7 6 5 4 3 2 1 0 RESERVED FLT_CLR R-0-0h W-0h Table 8-21. FLT_CLR Register Field Descriptions Bit Field Type Reset Description 15 RESERVED R/W 0h Reserved 14-1 RESERVED R-0 0h Reserved 0 FLT_CLR W 0h Clear latched faults 0h = No clear fault command is issued 1h = To clear the latched fault bits. This bit automatically resets after being written. www.ti.com DRV8317 SLVSGT3 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: DRV8317 |
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