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8.3.11.3.3 OCP Report Only (OCP_MODE = 011b)

No protective action occurs after an OCP event in this mode. The over current event is reported by driving the

nFAULT pin low and setting the FAULT, OCP bits (in DEV_STS register) and corresponding FETs' OCP bits

(in DRV_STS register) to 1b. DRV8317 continues to operate as usual. The external controller manages the

over current condition by acting appropriately. The reporting clears (nFAULT pin is released, FAULT, OCP, and

corresponding FETs' OCP bits are set to 0b) when a clear fault command is issued either through the FLT_CLR

bit or an nSLEEP reset pulse (tRST).

8.3.11.4 VM Over Voltage Protection (OVP)

If at any time, input supply voltage on the VM pin rises higher than the VOVP rising threshold, all the integrated

FETs are in Hi-Z, FAULT, OVP bits (in DEV_STS register) and VM_OV (in SUP_STS register) are set to 1b and

the nFAULT pin is driven low. Normal operation resumes automatically (pre-driver operation and the nFAULT pin

is released) once retry time (tRETRY) lapses after VM pin voltage is below the VOVP falling threshold as shown

inFigure 8-27. The FAULT, OVP and VM_OV bits stay set to 1b until clear fault command is issued either through

the FLT_CLR bit or an nSLEEP reset pulse (tRST).

Retry time (tRETRY) is set by,

• Slow retry time (SLOW_TRETRY) by configuring OVP_MODE to 00b

• Fast retry time (FAST_TRETRY) by configuring OVP_MODE to 01b

IN DRV8317H, OVP_MODE is set to 01b and FAST_TRETRY is fixed at 5-ms.

VOVP (min) falling

VOVP (max) falling

VOVP (max) rising

VOVP (min) rising

VVM

nFAULT

FETs ON

FETs OFF

FETs ON

Time

tRETRY

Figure 8-27. VM Over Voltage Protection

8.3.11.5 SPI Fault

In the event of a SPI transaction fault (parity, frame or bus contention error), if SPLIFLT_MODE is set to 0b,

nFAULT is driven low, FAULT, SPIFLT bits (in DEV_STS register) and SPI_PARITY/ BUS_CNT/ FRM_ERR bits

(in SYSIF_STS register) are set to 1b. DRV8317 continues to operate as usual. The external controller manages

the SPI fault event by acting appropriately. The reporting clears (nFAULT pin is released, FAULT, SPIFLT, and

SPI_PARITY/ BUS_CNT/ FRM_ERR bits are set to 0b) when a clear fault command is issued either through the

FLT_CLR bit or an nSLEEP reset pulse (tRST).

If SPIFLT_MODE is set to 1b, SPI fault is disabled and reporting (nFAULT, status register bits) does not happen

on a SPI fault event.

8.3.11.6 System (OTP Read) Fault

DRV8317 loads the configurable register settings from the OTP on every power-up cycle. If an OTP read

fault is encountered while configuring the registers, pre-driver is disabled, FAULT, SYSFLT bits (in DEV_STS

resumes (pre-driver, FAULT, SYSFLT, OTPLD_ERR bits set to 0b and nFAULT pin is released) when a clear

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DRV8317

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