DRV8317 datasheet(35/69 Pages) TI

35 / 69 page

Note

During power up and power down of the device through the nSLEEP pin, the nFAULT pin is held low

as the internal regulators are enabled or disabled. After the regulators have enabled or disabled, the

nFAULT pin is automatically released. The duration that the nFAULT pin is low does not exceed the

tSLEEP or tWAKE time.

8.4.1.2 Operating Mode

When the nSLEEP pin is high and the VVM voltage is greater than the VUVLO voltage, the device goes to

operating mode. The tWAKE time must elapse before the device is ready for inputs. In this mode the charge

pump, AVDD regulator and SPI bus are active.

8.4.1.3 Fault Reset (FLT_CLR or nSLEEP Reset Pulse)

In the case of latched faults, DRV8317 turns off the MOSFETs (Hi-Z) and the motor coasts to a stop.

When the fault condition clears, the device can go to the operating state again by either setting the FLT_CLR

bit to 1b in the SPI variant or by issuing a reset pulse on the nSLEEP pin in the hardware variant. The nSLEEP

reset pulse (tRST) consists of a high-to-low-to-high transition on the nSLEEP pin. The low period of the sequence

should fall with the tRST time window or else the device will start the complete shutdown sequence. The reset

pulse has no effect on any of the regulators, device settings, or other functional blocks.

8.5 SPI Communication

8.5.1 Programming

8.5.1.1 SPI Format

SPI Format - with Parity

The SDI input data word is 24 bits long and consists of the following format:

• 1 read or write bit, W (bit B23)

• 6 address bits, A (bits B22 through B17)

• Parity bit, P (bit B16)

• 15 data bits with 1 parity bit, D (bits B15 through B0)

The SDO output data word is 24 bits long. The most significant bits are status bits and the least significant 16

bits are the data content of the register being accessed.

Table 8-7. SDI Input Data Word Format for SPI

R/W

ADDRESS

PAR

ITY

PAR

ITY

DATA

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9

D14 D13 D12 D11 D10 D9

Table 8-8. SDO Output Data Word Format

STATUS

DATA

B23 B22 B21 B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9

B8 B7

S0 D15 D14 D13 D12 D11 D10 D9

D8 D7

The details of the bits used in SPI frame format are detailed below.

Read/Write Bit (R/W): R/W (W0) bit set to 0b indicates a SPI write transaction. For a SPI read operation, R/W

bit needs to be set to 1b.

Address Bits (A): A SPI secondary device takes a 6-bit register address.

Parity Bit (P): Both header and data fields of a SPI input data frame include a parity bit for single bit error

detection - in Table 8-7, B16 is parity bit for the header field, while B15 is the parity bit for the data field. The

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DRV8317

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