 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
DRV8317 数据表(PDF) 38 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
DRV8317 数据表(HTML) 38 Page - Texas Instruments |
|
|
38 / 69 page  8.6.1 DEV_STS Register (Offset = 0h) [Reset = 0280h] DEV_STS is shown in Figure 8-28 and described in Table 8-11. Return to the Table 8-9. Figure 8-28. DEV_STS Register 15 14 13 12 11 10 9 8 PARITY RESERVED DNRDY_STS SYSFLT R-0h R-0-0h R-0-1h R-0h 7 6 5 4 3 2 1 0 RESET SPIFLT OCP UVW OVP UVP OTF FAULT R-1h R-0h R-0h R-0h R-0h R-0h R-0h R-0h Table 8-11. DEV_STS Register Field Descriptions Bit Field Type Reset Description 15 PARITY R 0h Parity Bit if SPI_PEN is set to '1' otherwise reserved 14-10 RESERVED R-0 0h Reserved 9 DNRDY_STS R-0 1h Device not ready status 0h = Device is ready to spin motor 1h = Device is not ready 8 SYSFLT R 0h OTP read fault occurred. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP 0h = No OTP read fault is detected 1h = OTP read fault detected 7 RESET R 1h Device power on status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP 0h = Cleared by writing 1b to FLT_CLR bit after power-up 1h = Device has undergone power on reset 6 SPIFLT R 0h SPI fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP 0h = No SPI fault is detected 1h = SPI fault is detected 5 OCP R 0h Driver over current Status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP 0h = No over current condition is detected 1h = Over current condition is detected 4 UVW R 0h VM under voltage warning fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP 0h = No VM under voltage warn condition is detected 1h = VM under voltage warn condition is detected 3 OVP R 0h Over voltage status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP 0h = No over voltage condition is detected 1h = Over voltage condition is detected 2 UVP R 0h Supply under voltage status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP 0h = No under voltage condition is detected on VM or CP 1h = Under voltage condition is detected on VM or CP 1 OTF R 0h Over temperature fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP 0h = No over temperature warning / shutdown is detected 1h = Over temperature warning / shutdown is detected 0 FAULT R 0h Device fault status. Status remains latched until cleared by write to FLT_CLR or reset pulse on nSLEEP 0h = No fault condition is detected 1h = Fault condition is detected DRV8317 SLVSGT3 – DECEMBER 2022 www.ti.com 38 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8317 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
