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DRV8317 数据表(PDF) 48 Page - Texas Instruments |
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DRV8317 数据表(HTML) 48 Page - Texas Instruments |
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48 / 69 page ![]() 8.6.10 FLT_TCTRL Register (Offset = 16h) [Reset = 0003h] FLT_TCTRL is shown in Figure 8-37 and described in Table 8-20. Return to the Table 8-9. Figure 8-37. FLT_TCTRL Register 15 14 13 12 11 10 9 8 PARITY RESERVED R/W-0h R-0-0h 7 6 5 4 3 2 1 0 RESERVED SLOW_TRETRY FAST_TRETRY R-0-0h R/W-0h R/W-3h Table 8-20. FLT_TCTRL Register Field Descriptions Bit Field Type Reset Description 15 PARITY R/W 0h Parity Bit if SPI_PEN is set to '1' otherwise reserved 14-4 RESERVED R-0 0h Reserved 3-2 SLOW_TRETRY R/W 0h Retry time (typical) for slow recovery from fault condition 0h = 0.5s 1h = 1s 2h = 2s 3h = 5s 1-0 FAST_TRETRY R/W 3h Retry time (typical) for fast recovery from fault condition 0h = 0.5ms 1h = 1ms 2h = 2ms 3h = 5ms DRV8317 SLVSGT3 – DECEMBER 2022 www.ti.com 48 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8317 |
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