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DRV8317 数据表(PDF) 16 Page - Texas Instruments |
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DRV8317 数据表(HTML) 16 Page - Texas Instruments |
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16 / 69 page ![]() 8.2 Functional Block Diagram Predriver Stage nFAULT SDO SPI SCLK SDI nSCS Input Control AVDD AVDD AVDD RnFAULT SOC AV AV AV SOA Output Offset Bias SOB CSAREF INHA INLA INHB INLB INHC INLC I/O Control Output HS Pre- driver Power Stage VM PGND OUTA CP LS Pre- driver VLS Predriver Stage HS Pre- driver Power Stage VM PGND OUTB CP LS Pre- driver VLS Predriver Stage HS Pre- driver Power Stage VM PGND OUTC CP LS Pre- driver VLS Current Sense for Phase - A Current Sense for Phase - B Current Sense for Phase - C ISEN_A ISEN_B ISEN_C ISEN_A ISEN_B ISEN_C Current Sense Amplifiers Interface Overcurrent Protection VM, AVDD, CP, VIN_AVDD UVLO Protection VM Overvoltage Protection VM Undervoltage Warning Thermal Warning Thermal Shutdown Protection PGND Thermal PAD Digital Control Ext. Load AVDD Linear Regulator AVDD AGND Regulator VM VM CP + CVM1 CVM2 CCP Charge Pump VIN_AVDD CCSAREF CAVDD LS Predriver Power Supply Regulator VLS CFLY CPH CPL CVIN_AVDD1 CVIN_AVDD2 nSLEEP Figure 8-1. DRV8317S Functional Block Diagram DRV8317 SLVSGT3 – DECEMBER 2022 www.ti.com 16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8317 |
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