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parity scheme used is even parity - the number of ones in a block of 16-bits (including the parity bit) is even.

Data will be written to the internal registers only if the parity check is successful. Parity checks can be enabled or

disabled by configuring the SPI_PEN bit of SYS_CTRL register. Parity checks are disabled by default.

Note

Though parity checks are disabled by default, TI recommends enabling parity checks to safeguard

against single-bit errors.

Error Handling

Parity Error: Upon detecting a parity error, the secondary device responds in the following ways. Parity error

gets latched and reported on nFAULT. The error status is available for read on SPI_PARITY field of SYS_STS

SDO will be driven by the secondary device being addressed. Updates to write address pointer and the device

registers will be ignored when parity error is detected. In a sequential write, upon detection of parity error any

subsequent register writes will be ignored.

Frame Error: Any incomplete SPI Frame will be reported as Frame error. Frame errors will be latched in

FRM_ERR field of SYSIF_STS register and indicated on nFAULT.

SPI Read/Write Sequence

SPI Read Sequence: The SPI read transaction comprises of an 8-bit header (R/W - 1 bit, Address - 6 bits,

and party -1 bit) followed by 16-bit dummy data words. Upon receiving the first byte of header, the secondary

device responds with an 8-bit device status information. The read address pointer gets updated immediately

after receiving the address field of the header. The read address from the header acts as the starting address for

the register reads. The read address pointer gets incremented automatically upon completion of a 16-bit transfer.

The length of data transfer is not restricted by the secondary device. The secondary device responds with data

as long as the primary device transmits dummy words. If parity error check is enabled, the MSB of read data will

be replaced with computed parity bit

SPI Write Sequence: SPI write transaction comprises of an 8-bit header followed by 16-bit data words to be

written into the register bank. Similar to a read transaction, the addressed secondary device responds with an

8-bit device status information upon receiving the first byte of header. Once the header bytes are received,

the write address pointer gets updated. The write address from the header acts as the starting address for

sequential register writes. The read address pointer will retain the address of the register being read in the

previous SPI transaction. The length of data transfer is not restricted by the secondary device. Both read and

write address pointers will be incremented automatically upon completion of a 16-bit transfer. While receiving

data from the primary device, the SDO will be driven with the register data addressed by read address pointer.

DRV8317

SLVSGT3 – DECEMBER 2022

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