DRV8317 datasheet(61/69 Pages) TI

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11 Layout

11.1 Layout Guidelines

The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver

device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used

when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high

current.

Small-value capacitors should be ceramic, and placed closely to device pins including, AVDD, charge pump,

CSAREF, VINAVDD and VM.

The high-current device outputs should use wide metal traces.

To reduce noise coupling and EMI interference from large transient currents into small-current signal paths,

grounding should be partitioned between PGND and AGND. TI recommends connecting all non-power stage

circuitry (including the thermal pad) to AGND to reduce parasitic effects and improve power dissipation from

the device. Ensure grounds are connected through net-ties to reduce voltage offsets and maintain gate driver

performance. A common ground plane can also be used for PGND and AGND to minimize inductance in the

grounding, but it is recommended to place motor switching outputs as far away from analog and digital signals

so motor noise does not couple into the analog and digital circuits.

The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to

connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias helps dissipate

the heat that is generated in the device.

To improve thermal performance, maximize the ground area that is connected to the thermal pad ground across

all possible layers of the PCB. Using thick copper pours can lower the junction-to-air thermal resistance and

improve thermal dissipation from the die surface.

Figure 11-1 shows a recommended layout example.

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DRV8317

SLVSGT3 – DECEMBER 2022

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DRV8317 数据表(PDF) 61 Page - Texas Instruments