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DRV8317 数据表(PDF) 4 Page - Texas Instruments |
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DRV8317 数据表(HTML) 4 Page - Texas Instruments |
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4 / 69 page ![]() 6 Pin Configuration and Functions 36 35 34 33 32 31 30 29 nSLEEP nFAULT NC 1 2 3 4 5 6 7 8 9 10 CPL CPH CP VIN_AVDD VM VM PGND 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18 INLC INHC INLB INHB INLA INHA AVDD AGND VM PGND Thermal Pad Figure 6-1. DRV8317S 36-Pin WQFN With Exposed Thermal Pad Top View 36 35 34 33 32 31 30 29 nSLEEP nFAULT NC 1 2 3 4 5 6 7 8 9 10 CPL CPH CP VIN_AVDD VM VM PGND 28 27 26 25 24 23 22 21 20 19 11 12 13 14 15 16 17 18 INLC INHC INLB INHB INLA INHA AVDD AGND VM PGND Thermal Pad Figure 6-2. DRV8317H 36-Pin WQFN With Exposed Thermal Pad Top View Table 6-1. Pin Functions PIN 36-pin package TYPE (1) DESCRIPTION NAME DRV8317S DRV8317H AGND 21 21 GND Device analog ground. Connect to a separate ground plane. (1) AVDD 22 22 PWR O 3.3V regulator output. Connect a X5R or X7R, 2.2-µF (no load) or 4.7-µF (up to 80mA load), 6.3-V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 80 mA for external loads. CP 6 6 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the CP and VM pins. CPH 5 5 PWR Charge pump switching node. Connect a X5R or X7R, 100-nF, (2xVM)- rated ceramic capacitor between the CPH and CPL pins. CPL 4 4 PWR DRV8317 SLVSGT3 – DECEMBER 2022 www.ti.com 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: DRV8317 |
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