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DRV8317 数据表(PDF) 9 Page - Texas Instruments |
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DRV8317 数据表(HTML) 9 Page - Texas Instruments |
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9 / 69 page  TJ = –40°C to +150°C, VVM = 4.5 to 20 V (unless otherwise noted). Typical limits apply for TA = 25°C, VVM = 12 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tDEAD Dead time (high to low / low to high) VVM = 12V, SLEW_RATE = 00b (SPI Variant) or SLEW pin tied to AGND (HW Variant) 575 1500 ns VVM = 12V, SLEW_RATE = 01b (SPI Variant) or SLEW pin to 47 kΩ +/- 5% tied to AGND (HW Variant) 325 750 ns VVM = 12V, SLEW_RATE = 10b (SPI Variant) or SLEW pin to Hi-Z (HW Variant) 250 600 ns VVM = 12V, SLEW_RATE = 11b (SPI Variant) or SLEW pin tied to AVDD (HW Variant) 250 600 ns tPD Propagation delay (high-side / low-side ON/OFF) INHx = 1 to OUTx transisition, VVM = 12V, SLEW = 00b (SPI Variant) or SLEW pin tied to AGND (HW Variant) 1300 1750 ns INHx = 1 to OUTx transisition, VVM = 12V, SLEW = 01b (SPI Variant) or SLEW pin to 47 kΩ +/- 5% tied to AGND (HW Variant) 800 1050 ns INHx = 1 to OUTx transisition, VVM = 12V, SLEW = 10b (SPI Variant) or SLEW pin to Hi-Z (HW Variant) 450 600 ns INHx = 1 to OUTx transisition, VVM = 12V, SLEW = 11b (SPI Variant) or SLEW pin tied to AVDD (HW Variant) 425 500 ns tMIN_PULSE Minimum output pulse width SLEW = 11b (SPI Variant) or SLEW pin tied to AVDD (HW Variant) 500 ns CURRENT SENSE AMPLIFIER GCSA Current sense gain CSA_GAIN = 00b (SPI Variant) or GAIN pin tied to AGND (HW Variant) 0.25 V/A CSA_GAIN = 01b (SPI Variant) or GAIN pin to 47 kΩ +/- 5% tied to AGND (HW Variant) 0.5 V/A CSA_GAIN = 10b (SPI Variant) or GAIN pin to Hi-Z (HW Variant) 1 V/A CSA_GAIN = 11b (SPI Variant) or GAIN pin tied to AVDD (HW Variant) 2 V/A GCSA_ERR Current sense gain error TA = 25°C, IPHASE ≤ 2.5 A –3 3 % GCSA_ERR Current sense gain error TA = 25°C, 2.5 A < IPHASE ≤ 4 A –3.5 3.5 % GCSA_ERR Current sense gain error TA = 25°C, 4 A < IPHASE ≤ 5 A –3.5 4.5 % GCSA_ERR Current sense gain error IPHASE ≤ 2.5 A –4.5 4.5 % GCSA_ERR Current sense gain error 2.5 A < IPHASE ≤ 4 A –5 6 % GCSA_ERR Current sense gain error 4A < IPHASE ≤ 5 A –5 8 % IMATCH Current sense gain error matching between phases A, B and C TJ = 25°C –3 3 % –5 5 % FSPOS Full scale positive current measurement 5 A FSNEG Full scale negative current measurement –5 A VLINEAR SOX output voltage linear range 0.25 VREF – 0.25 V www.ti.com DRV8317 SLVSGT3 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: DRV8317 |
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