DRV8317 datasheet(37/69 Pages) TI

37 / 69 page

8.6 DRV8317 Registers

Table 8-9 lists the memory-mapped registers for the DRV8317 registers. All register offset addresses not listed in

Table 8-9 should be considered as reserved locations and the register contents should not be modified.

Table 8-9. DRV8317 Registers

Offset

Acronym

Section

DEV_STS

Device Status Register

Section 8.6.1

DEV_RSTS

Device Raw Status Register

Section 8.6.2

OT_STS

Over Temperature Status Register

Section 8.6.3

SUP_STS

Supply Status Register

Section 8.6.4

DRV_STS

Driver Status Register

Section 8.6.5

SYSIF_STS

System Interface Status Register

Section 8.6.6

10h

FLT_MODE

Fault Mode Register

Section 8.6.7

12h

SYSF_CTRL

System Fault Control Register

Section 8.6.8

13h

DRVF_TCTRL

Driver Fault Control Register

Section 8.6.9

16h

FLT_TCTRL

Fault Timing Control Register

Section 8.6.10

17h

FLT_CLR

Fault Clear Register

Section 8.6.11

18h

VMUV_WARN_THR

VM Under Voltage Warn Threshold Register

Section 8.6.12

20h

PWM_CTRL

PWM Control Register

Section 8.6.13

22h

DRV_CTRL

Predriver control Register

Section 8.6.14

23h

CSA_CTRL

CSA Control Register

Section 8.6.15

3Fh

SYS_CTRL

System Control Register

Section 8.6.16

Complex bit access types are encoded to fit into small table cells. Table 8-10 shows the codes that are used for

access types in this section.

Table 8-10. DRV8317 Access Type Codes

Access Type

Code

Description

Read Type

Read

R-0

-0

Read

Returns 0s

Write Type

Write

Reset or Default Value

-n

Value after reset or the default

value

www.ti.com

DRV8317

SLVSGT3 – DECEMBER 2022

Submit Document Feedback

Product Folder Links: DRV8317

DRV8317 数据表(PDF) 37 Page - Texas Instruments

DRV8317 数据表(HTML) 37 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69

数据表下载