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DRV8317 数据表(PDF) 29 Page - Texas Instruments |
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DRV8317 数据表(HTML) 29 Page - Texas Instruments |
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29 / 69 page  Table 8-6. Fault Action and Response (continued) FAULT CONDITION CONFIGURATION REPORT PRE-DRIVER FAULT STATUS BITS DIGITAL RECOVERY VM over voltage protection (VM_OV) VVM > VOVP (rising) OVP_MODE = 00b nFAULT Hi-Z Latched Active Automatic: SLOW_TRETRY and VVM < VOVP (falling) OVP_MODE = 01b nFAULT Hi-Z Latched Active Automatic: FAST_TRETRY and VVM < VOVP (falling) SPI fault (SPIFLT) SCLK fault and ADDR fault SPIFLT_MODE = 0b nFAULT Active Latched Active No action; report only mode SPIFLT_MODE = 1b — Active — Active — System (OTP read) (SYSFLT) OTP read parity fault — nFAULT Disabled Latched Active Latched: Cleared by FLT_CLR bit or nSLEEP reset pulse FET over temperature warning (OTW_FET) TJ > TOTW_FET OTF_MODE = 00b nFAULT Hi-Z Latched Active Automatic: SLOW_TRETRY and TJ < TOTW_FET - TOTW_FET_HYS OTF_MODE = 01b nFAULT Hi-Z Latched Active Automatic: FAST_TRETRY and TJ < TOTW_FET - TOTW_FET_HYS FET over temperature shutdown (OTS_FET) TJ > TOTS_FET OTF_MODE = 00b nFAULT Hi-Z Latched Active Automatic: SLOW_TRETRY and TJ < TOTS_FET - TOTS_FET_HYS OTF_MODE = 01b nFAULT Hi-Z Latched Active Automatic: FAST_TRETRY and TJ < TOTS_FET - TOTS_FET_HYS AVDD LDO over temperature shutdown (OTS_LDO) TJ > TOTS_LDO — — Hi-Z — Reset Automatic: TJ < TOTS_LDO - TOTS_LDO_HYS 8.3.11.1 Under Voltage Protection (UVP) DRV8317 has under voltage protection enabled for VM, VIN_AVDD, AVDD and CP voltage rails - these fault protections cannot be disabled. VM, VIN_AVDD and AVDD under voltage faults result in device reset; CP under voltage fault response is user configurable through UVP mode. VM, VIN_AVDD, AVDD Under Voltage Protection (VIN_AVDD_UV, AVDD_UV) If at any time, the voltage on VIN_AVDD or AVDD pin falls below the corresponding under voltage falling threshold (VVINAVDD_UV or VAVDD_UV), DRV8317 enters reset - in reset, FETs are in Hi-Z, pre-driver, charge pump, current sense amplifier and digital logic are disabled. Normal device operation resumes automatically after the respective rail voltage rises above the corresponding under voltage rising threshold (VVINAVDD_UV or VAVDD_UV) as shown in Figure 8-22. VUV (min) falling VUV (max) falling VUV (max) rising VUV (min) rising VVIN_AVDD, VAVDD DEVICE ON DEVICE RESET DEVICE ON Time Figure 8-22. VIN_AVDD, AVDD Under Voltage Protection VM, CP Under Voltage Protection (VM_UV, CP_UV) If at any time the voltage on VM or CP pin falls below the corresponding under voltage falling threshold (VVM_UV or VCP_UV), FETs are in Hi-Z, charge pump is disabled, nFAULT pin is driven low, FAULT and UVP in DEV_STS www.ti.com DRV8317 SLVSGT3 – DECEMBER 2022 Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: DRV8317 |
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