DSP56303 datasheet(255/292 Pages) FREESCALE

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Programming Sheets

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

B-11

Figure B-2. Operating Mode Register (OMR)

Central Processor

Operating Mode Register

Reset = $00030X; X = latched from levels on Mode pins

15 14 13 12 11 10

876

5432

EBD

19 18 17 16

21 20

BRT TAS

CPD0

= Reserved, Program as 0

EUN

APD ABE

Stack Extension Enable, Bit 20

0 = Stack extension disabled

1 = Stack extension enabled

Stack Extension Wrap Flag, Bit 19

0 = No stack extension wrap

1 = Stack extension wrap (sticky bit)

Stack Extension Overflow Flag, Bit 18

0 = No stack overflow

1 = Stack overflow

Stack Extension X Y Select, Bit 16

0 = Mapped to X memory

1 = Mapped to Y memory

Stack Extension Underflow Flag, Bit 17

0 = No stack underflow

1 = Stack underflow

0 = Enables external bus

1 = Disables external bus

External Bus Disable, Bit 4

0 = Delay is 128K clock cycles

1 = Delay is 16 clock cycles

Memory Switch Mode, Bit 7

0 = Memory switching disabled

CPD1

XYS

WRP EOV

SEN

Chip Operating Mode, Bits 3–0

Refer to the operating modes

Stop Delay Mode, Bit 6

1 = Memory switching enabled

Core-DMA Priority, Bits 9–8

TA Synchronize Select, Bit 11

0 = Not synchronized

1 = Synchronized

CPD[1:0]

Description

Compare SR[CP] to

active DMA channel

priority

DMA has higher

priority than core

DMA has same

priority as core

DMA has lower

priority than core

Cache Burst Mode Enable, Bit 10

0 = Burst Mode disabled

1 = Burst Mode enabled

Address Attribute Priority Disable, Bit 14

0 = Priority mechanism enabled

1 = Priority mechanism disabled

Bus Release Timing, Bit 12

0 = Fast Bus Release mode

1 = Slow Bus Release mode

Asynchronous Bus Arbitration Enable, Bit 13

0 = Synchronization disabled

1 = Synchronization enabled

table in Chapter 4.

*0 *0

ATE

Address Trace Enable, Bit 15

0 = Address Trace mode disabled

1 = Address Trace mode enabled

Application:

Date:

Programmer:

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