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DSP56303 数据表(PDF) 43 Page - Freescale Semiconductor, Inc |
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DSP56303 数据表(HTML) 43 Page - Freescale Semiconductor, Inc |
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43 / 292 page  JTAG/OnCE Interface DSP56303 User’s Manual, Rev. 2 Freescale Semiconductor 2-19 DE Input/Output Input Debug Event Provides a way to enter Debug mode from an external command controller (as input) or to acknowledge that the chip has entered Debug mode (as output). When asserted as an input, DE causes the DSP56300 core to finish the current instruction, save the instruction pipeline information, enter Debug mode, and wait for commands from the debug serial input line. When a debug request or a breakpoint condition cause the chip to enter Debug mode DE is asserted as an output for three clock cycles. DE has an internal pull-up resistor. DE is not a standard part of the JTAG Test Access Port (TAP) Controller. It connects to the OnCE module to initiate Debug mode directly or to provide a direct external indication that the chip has entered the Debug mode. All other interface with the OnCE module must occur through the JTAG port. This input is 5 V tolerant. Table 2-16. JTAG/OnCE Interface (Continued) Signal Name Type State During Reset Signal Description |
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