DSP56303 datasheet(38/292 Pages) FREESCALE

38 / 292 page

DSP56303 User’s Manual, Rev. 2

2-14

Freescale Semiconductor

Signals/Connections

SCK0

PC3

Input/Output

Input or Output

Ignored input

Serial Clock

Provides the serial bit rate clock for the ESSI interface for both the transmitter

and receiver in Synchronous modes, or the transmitter only in Asynchronous

modes.

Although an external serial clock can be independent of and asynchronous to

the DSP system clock, it must exceed the minimum clock cycle time of 6 T

(that is, the system clock frequency must be at least three times the external

ESSI clock frequency). The ESSI needs at least three DSP phases inside

each half of the serial clock.

Port C 3

The default configuration following reset is GPIO. For PC3, signal direction is

controlled through PRRC. This signal is configured as SCK0 or PC3 through

PCRC. This input is 5 V tolerant.

SRD0

PC4

Input

Input or Output

Ignored input

Serial Receive Data

Receives serial data and transfers the data to the ESSI receive shift register.

SRD0 is an input when data is being received.

Port C 4

The default configuration following reset is GPIO. For PC4, signal direction is

controlled through PRRC. This signal is configured as SRD0 or PC4 through

PCRC. This input is 5 V tolerant.

STD0

PC5

Output

Input or Output

Ignored input

Serial Transmit Data

Transmits data from the serial transmit shift register. STD0 is an output when

data is being transmitted.

Port C 5

The default configuration following reset is GPIO. For PC5, signal direction is

controlled through PRRC. This signal is configured as STD0 or PC5 through

PCRC. This input is 5 V tolerant.

Notes: 1.

In the Stop state, the signal maintains the last state as follows:

•

If the last state is input, the signal is an ignored input.

•

If the last state is output, these lines are tri-stated.

The Wait processing state does not affect the signal state.

Table 2-12. Enhanced Synchronous Serial Interface 0 (ESSI0) (Continued)

Signal

Name

Type

State During

Reset1, 2

Signal Description

DSP56303 数据表(PDF) 38 Page - Freescale Semiconductor, Inc

DSP56303 数据表(HTML) 38 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

DSP56303 数据表(PDF) 38 Page - Freescale Semiconductor, Inc

DSP56303 数据表(HTML) 38 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载