| 数据搜索系统,热门电子元器件搜索 |
|
DSP56303 数据表(PDF) 39 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
DSP56303 数据表(HTML) 39 Page - Freescale Semiconductor, Inc |
|
39 / 292 page ![]() Enhanced Synchronous Serial Interface 1 (ESSI1) DSP56303 User’s Manual, Rev. 2 Freescale Semiconductor 2-15 2.9 Enhanced Synchronous Serial Interface 1 (ESSI1) Table 2-13. Enhanced Synchronous Serial Interface 1 (ESSI1) Signal Name Type State During1 Signal Description Reset Stop SC10 PD0 Input or Output Input Disconnected internally Serial Control 0 Functions in either Synchronous or Asynchronous mode. For Asynchronous mode, this signal is the receive clock I/O (Schmitt-trigger input). For Synchronous mode, this signal is either for Transmitter 1 output or Serial I/O Flag 0. Port D 0 The default configuration following reset is GPIO. For PD0, signal direction is controlled through the Port D Direction Register (PRRD). This signal is configured as SC10 or PD0 through the Port D Control Register (PCRD). This input is 5 V tolerant. SC11 PD1 Input/Output Input or Output Input Disconnected internally Serial Control 1 Functions in either Synchronous or Asynchronous mode. For Asynchronous mode, this signal is the receiver frame sync I/O. For Synchronous mode, this signal is either Transmitter 2 output or Serial I/O Flag 1. Port D 1 The default configuration following reset is GPIO. For PD1, signal direction is controlled through PRRD. This signal is configured as SC11 or PD1 through PCRD. This input is 5 V tolerant. SC12 PD2 Input/Output Input or Output Input Disconnected internally Serial Control Signal 2 The frame sync for both the transmitter and receiver in Synchronous mode, and for the transmitter only in Asynchronous mode. When configured as an output, this signal is the internally generated frame sync signal. When configured as an input, this signal receives an external frame sync signal for the transmitter (and the receiver in synchronous operation). Port D 2 The default configuration following reset is GPIO. For PD2, signal direction is controlled through PRRD. This signal is configured as SC12 or PD2 through PCRD. This input is 5 V tolerant. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |