DSP56303 datasheet(67/292 Pages) FREESCALE

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Central Processor Unit (CPU) Registers

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

4-9

DO FOREVER Flag

Set when a DO FOREVER loop executes. The FV flag, like the LF flag, is

restored from the stack when a DO FOREVER loop terminates. Stacking and

restoring the FV flag when initiating and exiting a DO FOREVER loop,

respectively, allow program loops to be nested. When returning from the long

interrupt with an RTI instruction, the system stack is pulled and the value of

the FV bit is restored.

Do Loop Flag

When a program loop is in progress, enables the detection of the end of the

loop. The LF is restored from stack when a program loop terminates. Stacking

and restoring the LF when initiating and exiting a program loop, respectively,

allow program loops to be nested. When returning from the long interrupt with

an RTI instruction, the System Stack is pulled and the LF bit value is restored.

Double-Precision Multiply Mode

Enables four multiply/MAC operations to implement a double-precision

algorithm that multiplies two 48-bit operands with a 96-bit result. Clearing the

DM bit disables the mode.

The Double-Precision Multiply mode is supported to maintain object code

compatibility with devices in the DSP56000 family. For a more efficient way of

executing double precision multiply, refer to the chapter on the Data Arithmetic

Logic Unit in the DSP56300 Family Manual.

In Double-Precision Multiply mode, the behavior of the four specific operations

listed in the double-precision algorithm is modified. Therefore, do not use

these operations (with those specific register combinations) in

Double-Precision Multiply mode for any purpose other than the double

precision multiply algorithm. All other Data ALU operations (or the four listed

operations, but with other register combinations) can be used.

The double-precision multiply algorithm uses the Y0 Register at all stages.

Therefore, do not change Y0 when running the double-precision multiply

algorithm. If the Data ALU must be used in an interrupt service routine, Y0

should be saved with other Data ALU registers to be used and restored before

the interrupt routine terminates.

Sixteen-Bit Compatibility Mode

Affects addressing functionality, enabling full compatibility with object code

written for the DSP56000 family. When SC is set, MOVE operations to/from

any of the following PCU registers clear the eight MSBs of the destination: LA,

LC, SP, SSL, SSH, EP, SZ, VBA and SC. If the source is either the SR or

OMR, then the eight MSBs of the destination are also cleared. If the

destination is either the SR or OMR, then the eight MSBs of the destination

are left unchanged. To change the value of one of the eight MSBs of the SR or

OMR, clear SC.

SC also affects the contents of the Loop Counter Register. If SC is cleared

(normal operation), then a loop count value of zero causes the loop body to be

skipped, and a loop count value of $FFFFFF causes the loop to execute the

maximum number of 224 – 1 times. If the SC bit is set, a loop count value of

zero causes the loop to execute 216 times, and a loop count value of $FFFFFF

causes the loop to execute 216 – 1 times.

Note:

Due to pipelining, a change in the SC bit takes effect only after three

instruction cycles. Insert three NOP instructions after the instruction

that changes the value of this bit to ensure proper operation.

Table 4-2. Status Register Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

Description

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