DSP56303 datasheet(71/292 Pages) FREESCALE

71 / 292 page

Central Processor Unit (CPU) Registers

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

4-13

EUN

Stack Extension Underflow Flag

Set when a stack underflow occurs in Extended Stack mode. Extended stack

underflow is recognized when a pull operation is requested, SP = 0, and the

SEN bit enables Extended mode. The EUN flag is a sticky bit (that is, cleared

only by hardware reset or by an explicit MOVEC operation to the OMR).

Transition of the EUN flag from zero to one causes a Priority Level 3

(Non-maskable) stack error exception.

NOTE: While the chip is in Extended Stack mode, the UF bit in the SP acts

like a normal counter bit.

XYS

Stack Extension XY Select

Determines whether the stack extension is mapped onto X or Y memory

space. If the bit is clear, then the stack extension is mapped onto the X

memory space. If the XYS bit is set, the stack extension is mapped to the Y

memory space.

ATE

Address Trace Enable

When set, the Address Trace Enable (ATE) bit enables Address Trace

mode. The Address Trace mode is a debugging tool that reflects internal

memory accesses at the external bus address.

APD

Address Attribute Priority Disable

Disables the priority assigned to the Address Attribute signals (AA[0–3]).

When APD = 0 (default setting), the four Address Attribute signals each have

a certain priority: AA3 has the highest priority, AA0 has the lowest priority.

Therefore, only one AA signal can be active at one time. This allows

continuous partitioning of external memory; however, certain functions, such

as using the AA signals as additional address lines, require the use of

additional interface hardware. When APD is set, the priority mechanism is

disabled, allowing more than one AA signal to be active simultaneously.

Therefore, the AA signals can be used as additional address lines without

the need for additional interface hardware. For details on the Address

Attribute Registers, see Section 4.6.3, Address Attribute Registers

(AAR[0–3]), on page 4-26.

ABE

Asynchronous Bus Arbitration Enable

Eliminates the setup and hold time requirements for BB and BG, and

substitutes a required non-overlap interval between the deassertion of one

BG input to a DSP56300 family device and the assertion of a second BG

input to a second DSP56300 family device on the same bus. When the ABE

bit is set, the BG and BB inputs are synchronized. This synchronization

causes a delay between a change in BG or BB until this change is actually

accepted by the receiving device.

BRT

Bus Release Timing

Selects between fast or slow bus release. If BRT is cleared, a Fast Bus

Release mode is selected (that is, no additional cycles are added to the

access and BB is not guaranteed to be the last Port A pin that is tri-stated at

the end of the access). If BRT is set, a Slow Bus Release mode is selected

(that is, an additional cycle is added to the access, and BB is the last Port A

pin that is tri-stated at the end of the access).

TAS

TA Synchronize Select

Selects the synchronization method for the input Port A pin—TA (Transfer

Acknowledge). If TAS is cleared, you are responsible for asserting the TA

pin in synchrony with the chip clock, as described in the technical data sheet.

If TAS is set, the TA input pin is synchronized inside the chip, thus

eliminating the need for an off-chip synchronizer. Note that the TAS bit has

no effect when the TA pin is deasserted: you are responsible for deasserting

the TA pin in synchrony with the chip clock, regardless of the value of TAS.

Table 4-3. Operating Mode Register (OMR) Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

Description

DSP56303 数据表(PDF) 71 Page - Freescale Semiconductor, Inc

DSP56303 数据表(HTML) 71 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载