DSP56303 datasheet(46/292 Pages) FREESCALE

46 / 292 page

DSP56303 User’s Manual, Rev. 2

3-2

Freescale Semiconductor

Memory Configuration

3.1.1 Internal Program Memory

The default internal program memory consists of a 24-bit-wide, high-speed, SRAM occupying

the lowest 4 K (default), 3 K, 2 K, or 1 K locations in program memory space, depending on the

settings of the OMR[MS] and (SR[CE]) bits. Section 4.3.2, Operating Mode Register (OMR), on

page 1-15 provides details on the MS bit. Section 4.3.1, Status Register (SR), on page 1-9

provides details on the CE bit. The default internal program RAM is organized in 16 banks with

256 locations each (4 K). Setting the MS bit switches four banks of program memory to the X

data memory and an additional four banks of program memory to the Y data memory. Setting the

CE bit switches four banks of internal program memory to the Instruction Cache and reassigns its

address to external program memory. The memory addresses for the Instruction Cache vary

depending on the setting of the MS and CE bits. Section 3.6 provides a summary of the internal

RAM configurations. Refer to the memory maps for detailed information.

3.1.2 Memory Switch Modes—Program Memory

Memory switch mode allows reallocation of portions of program RAM to X and Y data RAM.

OMR[7] is the memory switch (MS) bit that controls this function, as follows:

When the MS bit is cleared, program memory consists of the default 4 K × 24-bit memory

space described in the previous section. In this default mode, the lowest external program

memory location is $1000. If the CE bit is set, the program memory consists of the lowest

3 K

× 24-bits of memory space and the lowest external program memory location is

$0C00.

When the MS bit is set, the highest 2 K × 24-bit portion of the internal program memory is

switched to internal X and Y data memory. In this mode, the lowest external program

memory location is $800. If the CE bit is set and the MS bit is set, the program memory

consists of the lowest 1 K

× 24-bits of memory space and the lowest external program

memory location is $400.

3.1.3 Instruction Cache

In program memory space, the location of the internal Instruction Cache (when enabled by the

CE bit) varies depending on the setting of the MS bit, as noted above. Refer to the memory maps

for detailed address information. When the instruction cache is enabled (that is, the SR[CE] bit is

set), 1 K program words switch to instruction cache and are not accessible via addressing; the

address range switches to external program memory.

3.1.4 Program Bootstrap ROM

The program memory space occupying locations $FF0000–$FF00BF includes the internal

bootstrap ROM. This ROM contains the 192-word DSP56303 bootstrap program.

DSP56303 数据表(PDF) 46 Page - Freescale Semiconductor, Inc

DSP56303 数据表(HTML) 46 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载