DSP56303 datasheet(87/292 Pages) FREESCALE

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DMA Control Registers 5–0 (DCR[5–0])

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

4-29

21–19

DTM

DMA Transfer Mode

Specify the operating modes of the DMA channel, as follows:

DTM[2–0

]

Trigger

Cleared

After

Transfer Mode

000

request

Yes

Block Transfer—DE enabled and DMA request

initiated. The transfer is complete when the counter

decrements to zero and the DMA controller reloads the

counter with the original value.

001

request

Yes

Word Transfer—A word-by-word block transfer (length

set by the counter) that is DE enabled. The transfer is

complete when the counter decrements to zero and the

DMA controller reloads the counter with the original

value.

010

request

Yes

Line Transfer—A line by line block transfer (length set

by the counter) that is DE enabled. The transfer is

complete when the counter decrements to zero and the

DMA controller reloads the counter with the original

value.

011

Yes

Block Transfer—The DE-initiated transfer is complete

when the counter decrements to zero and the DMA

controller reloads the counter with the original value.

100

request

Block Transfer—The transfer is enabled by DE and

initiated by the first DMA request. The transfer is

completed when the counter decrements to zero and

reloads itself with the original value. The DE bit is not

cleared at the end of the block, so the DMA channel

waits for a new request.

NOTE: The DMA End-of-Block-Transfer Interrupt

cannot be used in this mode.

101

request

Word Transfer—The transfer is enabled by DE and

initiated by every DMA request. When the counter

decrements to zero, it is reloaded with its original

value. The DE bit is not automatically cleared, so the

DMA channel waits for a new request.

NOTE: The DMA End-of-Block-Transfer Interrupt

cannot be used in this mode.

110

Reserved

111

Reserved

Note:

When DTM = 001 or 101, some peripherals can generate a second DMA request while the DMA controller is still

processing the first request (see the description of the DRS bits).

Table 4-11. DMA Control Register (DCR) Bit Definitions (Continued)

Bit

Number

Bit Name

Reset

Value

Description

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