DSP56303 datasheet(60/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

4-2

Freescale Semiconductor

Core Configuration

Table 4-1. DSP56303 Operating Modes

Mode

MODD

MODC

MODB

MODA

Reset

Vector

Description

000

$C00000

Expanded mode

Bypasses the bootstrap ROM, and the DSP56303 starts fetching

instructions beginning at address $C00000. Memory accesses

are performed using SRAM memory access type with 31 wait

states and no address attributes selected (default). Address

$C00000 is reflected as address $00000 on Port A signals

A[0–17].

000

$FF0000

Bootstrap from byte-wide memory

The bootstrap program loads a program RAM segment from

consecutive byte-wide P memory locations, starting at

P:$D00000 (bits 7–0). The memory is selected by the Address

Attribute AA1 and is accessed with 31 wait states. The EPROM

bootstrap code reads 3 bytes specifying the number of program

words, 3 bytes specifying the address to start loading the

program words, and then 3 bytes for each program word to be

loaded. The number of words, the starting address and the

program words are read LSB first followed by the mid and then

the MSB. The program words are condensed into 24-bit words

and stored in contiguous PRAM memory locations from the

specified starting address. Program execution starts from the

same address where loading started.

001

$FF0000

Bootstrap through SCI

The DSP is configured to load the program RAM from the SCI

interface. The number of program words to be loaded and the

starting address must be specified. The SCI bootstrap code

expects to receive 3 bytes specifying the number of program

words, 3 bytes specifying the address to start loading the

program words and then 3 bytes for each program word to be

loaded. The number of words, the starting address and the

program words are received least significant byte first followed

by the mid and then by the most significant byte. After receiving

the program words, program execution starts in the same

address where loading started. The SCI is programmed to work

in asynchronous mode with 8 data bits, 1 stop bit and no parity.

The clock source is external and the clock frequency must be

16x the baud rate. After each byte is received, it is echoed back

through the SCI transmitter.

$FF0000

Reserved

010

$FF0000

HI08 bootstrap in ISA/DSP563xx mode

The HI08 is configured to load the program RAM from the Host

Interface programmed to operate in the ISA mode. The HOST

ISA bootstrap code expects to read a 24-bit word specifying the

number of program words, a 24-bit word specifying the address

to start loading the program words and then a 24-bit word for

each program word to be loaded. The program words are stored

in contiguous P RAM memory locations starting at the specified

starting address. After reading the program words, program

execution starts from the same address where loading started.

The Host Interface bootstrap load program may be stopped by

setting the Host Flag 0 (HF0). This starts execution of the loaded

program from the specified starting address.

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