DSP56303 datasheet(68/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

4-10

Freescale Semiconductor

Core Configuration

Reserved. Write to 0 for future compatibility.

11–10

S[1–0]

Scaling Mode

Specify the scaling to be performed in the Data ALU shifter/limiter and the

rounding position in the Data ALU MAC unit. The Shifter/limiter Scaling mode

affects data read from the A or B accumulator registers out to the X-data bus

(XDB) and Y-data bus (YDB). Different scaling modes can be used with the

same program code to allow dynamic scaling. One application of dynamic

scaling is to facilitate block floating-point arithmetic. The scaling mode also

affects the MAC rounding position to maintain proper rounding when different

portions of the accumulator registers are read out to the XDB and YDB.

Scaling mode bits are cleared at the start of a long Interrupt Service Routine

and during a hardware reset.

Scaling

Mode

Rounding Bit

SEquation

No scaling

S = (A46 XOR A45)

OR (B46 XOR B45)

OR S (previous)

Scale down

S = (A47 XOR A46)

OR (B47 XOR B46)

OR S (previous)

Scale up

S = (A45 XOR A44)

OR (B45 XOR B44)

OR S (previous)

Reserved

—

S undefined

9–8

I[1–0]

Interrupt Mask

Reflect the current Interrupt Priority Level (IPL) of the processor and indicate

the IPL needed for an interrupt source to interrupt the processor. The current

IPL of the processor can be changed under software control. The interrupt

mask bits are set during hardware reset, but not during software reset.

Priority

Exceptions

Permitted

Exceptions Masked

Lowest

IPL 0, 1, 2, 3

None

IPL 1, 2, 3

IPL 0

IPL 2, 3

IPL 0, 1

Highest

IPL 3

IPL 0, 1, 2

7S0

Scaling

Set when a result moves from accumulator A or B to the XDB or YDB buses

(during an accumulator to memory or accumulator to register move) and

remains set until explicitly cleared; that is, the S bit is a sticky bit. The logical

equations of this bit are dependent on the Scaling mode. The scaling bit is set

if the absolute value in the accumulator, before scaling, is > 0.25 or < 0.75.

6L0

Limit

Set if the overflow bit is set or if the data shifter/limiter circuits perform a

limiting operation. In Arithmetic Saturation mode, the L bit is also set when an

arithmetic saturation occurs in the Data ALU result; otherwise, it is not

affected. The L bit is cleared only by a processor reset or by an instruction that

specifically clears it (that is, a sticky bit); this allows the L bit to be used as a

latching overflow bit. The L bit is affected by data movement operations that

read the A or B accumulator registers.

Table 4-2. Status Register Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

Description

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