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Bus Interface Unit (BIU) Registers

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

4-21

4.6 Bus Interface Unit (BIU) Registers

The three Bus Interface Unit (BIU) registers configure the external memory expansion port (Port

A). They include the following:

Bus Control Register (BCR)

DRAM Control Register (DCR)

Address Attribute Registers (AAR[3–0])

To use Port A correctly, configure these registers as part of the bootstrap process. The following

subsections describe these registers.

4.6.1 Bus Control Register (BCR)

The Bus Control Register (BCR), depicted in Figure 4-6, is a read/write register that controls the

external bus activity and Bus Interface Unit (BIU) operation. All BCR bits except bit 21, BBS,

are read/write bits. The BCR bits are defined in Table 4-8.

Figure 4-6. Bus Control Register (BCR)

XTLR

Crystal Range

Controls the internal crystal oscillator transconductance. The XTLR bit is

cleared (0) during hardware reset.

14–12

DF[2–0]

Division Factor

Define the DF of the low-power divider. These bits specify the DF as a power

of two in the range from 20 to 27.

11–0

MF[11–0]

PLL Multiplication Factor

Define the multiplication factor that is applied to the PLL input frequency. The

MF bits are cleared during hardware reset and thus correspond to an MF of

one.

BRH

BBS

BDFW4

BDFW3

BDFW2

BDFW1

BDFW0

BA3W2

BA3W1

BA3W0

BA2W2

876543

210

BA2W1

BA2W0

BA1W4

BA1W3

BA1W2

BA1W1

BA1W0

BA0W4

BA0W3

BA0W2

BA0W1

BA0W0

Reserved bit. Read as zero; write to zero for future compatibility

Table 4-7. PLL Control Register (PCTL) Bit Definitions (Continued)

Bit Number

Bit Name

Reset Value

Description

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