DSP56303 datasheet(70/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

4-12

Freescale Semiconductor

Core Configuration

4.3.2 Operating Mode Register (OMR)

The OMR is a read/write register divided into three byte-sized units. The lowest two bytes (EOM

and COM) control the chip’s operating mode. The high byte (SCS) controls and monitors the

stack extension. The OMR control bits are shown in Figure 4-2.

The Enhanced Operating Mode (EOM) and Chip Operating Mode (COM) bytes are affected only

by processor reset and by instructions directly referencing the OMR (that is, ANDI, ORI, and

other instructions, such as MOVEC, that specify OMR as a destination). The Stack

Control/Status (SCS) byte is referenced implicitly by some instructions, such as DO, JSR, and

RTI, or directly by the MOVEC instruction. During processor reset, the chip operating mode bits

(MD, MC, MB, and MA) are loaded from the external mode select pins MODD, MODC,

MODB, and MODA respectively. Table 4-3 defines the DSP56303 OMR bits.

Stack Control/Status (SCS)

Extended Operating Mode (EOM)

Chip Operating Mode (COM)

SEN WRP EOV EUN XYS ATE APD ABE BRT TAS BE CDP[1–0]

EBD MD MC MB MA

Reset:

000

00000

After reset, these bits reflect the corresponding value of the mode input (that is, MODD, MODC, MODB, or MODA,

respectively).

Reserved bit. Read as zero; write to zero for future compatibility

Figure 4-2. Operating Mode Register (OMR)

Table 4-3. Operating Mode Register (OMR) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

23–21

Reserved. Write to 0 for future compatibility.

SEN

Stack Extension Enable

Enables/disables the stack extension in data memory. If the SEN bit is set,

the extension is enabled. Hardware reset clears this bit, so the default out of

reset is a disabled stack extension.

WRP

Stack Extension Wrap Flag

Set when copying from the internal hardware stack (System Stack Register

file) to the stack extension memory begins. You can use this flag during the

debugging phase of the software development to evaluate and increase the

speed of software-implemented algorithms. The WRP flag is a sticky bit (that

is, cleared only by hardware reset or by an explicit MOVEC operation to the

OMR).

EOV

Stack Extension Overflow Flag

Set when a stack overflow occurs in Stack Extended mode. Extended stack

overflow is recognized when a push operation is requested while SP = SZ

(Stack Size register), and the Extended mode is enabled by the SEN bit. The

EOV flag is a sticky bit (that is, cleared only by hardware reset or by an

explicit MOVEC operation to the OMR). The transition of the EOV flag from

zero to one causes a Priority Level 3 (Non-maskable) stack error exception.

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