DSP56303 datasheet(96/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

5-4

Freescale Semiconductor

Programming the Peripherals

Configuring interrupts requires two steps:

Setting up the interrupt routine

The interrupt handler is located at the interrupt starting address.

The interrupt routines can be short (only two opcodes long) or long (more than two

opcodes and requiring a JSR instruction).

Enabling the interrupts

Set the corresponding bits in the applicable peripheral control register.

Enable peripheral interrupts in the Interrupt Priority Register (IPRP).

Enable global interrupts in the Mode Register (MR) portion of the Status Register

(SR).

Events that change bits in the peripheral control registers can then trigger the interrupt.

Depending on the peripheral, from two to six peripheral interrupt sources are available to the

programmer.

Example 5-2 shows a short interrupt programmed for the HI08. The main program enables the

Host Receive Interrupt in the Host Control Register (HCR). When the interrupt is triggered

during code execution, the core processing jumps to the Host Receive Interrupt routine location

at p:$60 and executes the code there. Since this is a short interrupt, the core returns to normal

code execution after executing the two move instructions, and an RTI instruction is not

necessary.

Example 5-2. Interrupts

bset#M_HRIE,x:M_HCR ; enable host receive interrupt

; Short Interrupt Routine

orgP:$60

movepx:M_HRX,x1

; HI08 Receive Data Full interrupt

movex1,y:(r0)+

5.4.3 DMA

The Direct Memory Access (DMA) controller permits data transfers between internal/external

memory and/or internal/external I/O in any combination without the intervention of the

DSP56303 core. Dedicated DMA address and data buses and internal memory partitioning

ensure that a high level of isolation is achieved so the DMA operation does not interfere with the

core operation or slow it down. The DMA moves data to/from the peripheral transmit/receive

registers. The programmer can use the DMA control registers to configure sources and

destinations of data transfers. Depending on the peripheral, one to four peripheral request sources

are available. This is the most efficient method of data transfer available. Core intervention is not

required after the DMA channel is initialized.

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