DSP56303 datasheet(30/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

2-6

Freescale Semiconductor

Signals/Connections

2.5.2 External Data Bus

2.5.3 External Bus Control

Table 2-7. External Data Bus Signals

Signal

Name

Type

State During Reset,

Stop, or Wait

Signal Description

D[0–23]

Input/Output

Tri-stated

Data Bus

When the DSP is the bus master, D[0–23] provide the bidirectional

data bus for external program and data memory accesses. Otherwise,

D[0–23] are tri-stated.

Table 2-8. External Bus Control Signals

Signal

Name

Type

State During Reset,

Stop, or Wait

Signal Description

AA0/RAS0–

AA3/RAS3

Output

Tri-stated

Address Attribute or Row Address Strobe

As AA, these signals function as chip selects or additional address lines.

Unlike address lines, however, the AA lines do not hold their state after a

read or write operation. As RAS, these signals can be used for Dynamic

Random Access Memory (DRAM) interface. These signals have

programmable polarity.

Output

Tri-stated

Read Enable

When the DSP is the bus master, RD is asserted to read external memory

on the data bus (D[0–23]). Otherwise, RD is tri-stated.

Output

Tri-stated

Write Enable

When the DSP is the bus master, WR is asserted to write external

memory on the data bus (D[0–23]). Otherwise, WR is tri-stated.

Input

Ignored Input

Transfer Acknowledge

If the DSP56303 is the bus master and there is no external bus activity, or

the DSP56303 is not the bus master, the

TA input is ignored. The TA input

is a Data Transfer Acknowledge (DTACK) function that can extend an

external bus cycle indefinitely. Any number of wait states (1, 2,..., infinity)

can be added to the wait states inserted by the BCR by keeping TA

deasserted. In typical operation,

TA is deasserted at the start of a bus

cycle, asserted to enable completion of the bus cycle, and deasserted

before the next bus cycle. The current bus cycle completes one clock

period after TA is asserted synchronous to CLKOUT. The number of wait

states is determined by the TA input or by the Bus Control Register (BCR),

whichever is longer. The BCR can set the minimum number of wait states

in external bus cycles.

To use the TA functionality, the BCR must be programmed to at least one

wait state. A zero wait state access cannot be extended by TA

deassertion; otherwise improper operation may result.

TA can operate

synchronously or asynchronously, depending on the setting of the TAS bit

in the Operating Mode Register (OMR).

TA functionality cannot be used during DRAM-type accesses; otherwise

improper operation may result.

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