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DSP56300 Core Functional Blocks

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

1-9

1.6.5 JTAG TAP and OnCE Module

In the DSP56300 core is a dedicated user-accessible TAP that is fully compatible with the IEEE

1149.1 Standard Test Access Port and Boundary Scan Architecture. Problems with testing

high-density circuit boards led to the development of this standard under the sponsorship of the

Test Technology Committee of IEEE and the JTAG. The DSP56300 core implementation

supports circuit-board test strategies based on this standard. The test logic includes a TAP with

four dedicated signals, a 16-state controller, and three test data registers. A boundary scan

static logic design, is independent of the device system logic. For details on the JTAG port,

consult the DSP56300 Family Manual.

The OnCE module interacts with the DSP56300 core and its peripherals nonintrusively so that

you can examine registers, memory, or internal peripherals. This facilitates hardware and

software development on the DSP56300 core processor. OnCE module functions are provided

through the JTAG TAP signals. For details on the OnCE module, consult the DSP56300 Family

Manual.

1.6.6 Internal Memory

The memory space of the DSP56300 core is partitioned into program, X data, and Y data

memory space. The data memory space is divided into X and Y data memory in order to work

with the two address ALUs and to feed two operands simultaneously to the data ALU. Memory

space includes internal RAM and ROM and can be expanded off-chip under software control. For

details on internal memory, see Chapter 3, Memory Configuration. Program RAM, instruction

cache, X data RAM, and Y data RAM size are programmable, as shown in Table 1-2.

There is an internal 192

× 24-bit bootstrap ROM.

1.6.7 External Memory Expansion

Memory can be expanded externlly as follows:

Data memory expansion to two 256 K × 24-bit word memory spaces using the standard

external address lines

Table 1-3. Internal Memory

Instruction

Cache

Switch

Mode

Program RAM

Size

Instruction

Cache Size

X Data RAM Size

Y Data RAM Size

disabled

4096

× 24-bit

2048

× 24-bit

2048

× 24-bit

enabled

disabled

3072

× 24-bit

1024

× 24-bit

2048

× 24-bit

2048

× 24-bit

disabled

enabled

2048

× 24-bit

3072

× 24-bit

3072

× 24-bit

enabled

1024

× 24-bit

1024

× 24-bit

3072

× 24-bit

3072

× 24-bit

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