DSP56303 datasheet(78/292 Pages) FREESCALE

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DSP56303 User’s Manual, Rev. 2

4-20

Freescale Semiconductor

Core Configuration

4.5 PLL Control Register (PCTL)

The bootstrap program must initialize the system Phase-Lock Loop (PLL) circuit by configuring

the PLL Control Register (PCTL). The PCTL is an X-I/O mapped, read/write register that directs

the internal PLL operation. (See Figure 4-5.)

Table 4-7 defines the DSP56303 PCTL bits. Changing the following bits may cause the PLL to

lose lock and re-lock according to the new value: PD[3–0], PEN, XTLR, and MF.

TIMER0 compare interrupt

TIMER1 overflow interrupt

TIMER1 compare interrupt

TIMER2 overflow interrupt

Lowest

TIMER2 compare interrupt

PD3

PD2

PD1

PD0

COD

PEN

PSTP

XTLD

XTLR

DF2

DF1

DF0

987

6543210

MF11

MF10

MF9

MF8

MF7

MF6

MF5

MF4

MF3

MF2

MF1

MF0

Figure 4-5. PLL Control Register (PCTL)

Table 4-7. PLL Control Register (PCTL) Bit Definitions

Bit Number

Bit Name

Reset Value

Description

23–20

PD[3–0]

Predivider Factor

Define the predivision factor (PDF) to be applied to the PLL input frequency.

The PD[3–0] bits are cleared during DSP56303 hardware reset, which

corresponds to a PDF of one.

COD

Clock Output Disable

Controls the output buffer of the clock at the CLKOUT pin. When COD is set,

the CLKOUT output is pulled high. When COD is cleared, the CLKOUT pin

provides a 50 percent duty cycle clock.

PEN

Set to PINIT

input value

PLL Enable

Enables PLL operation.

PSTP

PLL Stop State

Controls PLL and internal crystal oscillator behavior during the stop processing

state.

XTLD

XTAL Disable

Controls the internal crystal oscillator XTAL output. The XTLD bit is cleared

during DSP56303 hardware reset, so the XTAL output signal is active,

permitting normal operation of the crystal oscillator.

Table 4-6. Interrupt Source Priorities Within an IPL (Continued)

Priority

Interrupt Source

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