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Interrupt and Mode Control

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

2-7

2.6 Interrupt and Mode Control

The interrupt and mode control signals select the chip’s operating mode as it comes out of

hardware reset. After RESET is deasserted, these inputs are hardware interrupt request lines.

Output

(deasserted)

State during Stop/Wait

depends on the BRH

bit setting:

• BRH = 0: Output,

deasserted.

• BRH = 1: Maintains

last state (that is, if

asserted, remains

asserted)

Bus Request

Asserted when the DSP requests bus mastership and deasserted when

the DSP no longer needs the bus. BR can be asserted or deasserted

independently of whether the DSP56303 is a bus master or a bus slave.

Bus “parking” allows BR to be deasserted even though the DSP56303 is

the bus master (see the description of bus “parking” in the BB signal

description). The Bus Request Hold (BRH) bit in the BCR allows

BR to be

asserted under software control, even though the DSP does not need the

bus. BR is typically sent to an external bus arbitrator that controls the

priority, parking and tenure of each master on the same external bus. BR

is affected only by DSP requests for the external bus, never for the

internal bus. During hardware reset, BR is deasserted and the arbitration

is reset to the bus slave state.

Input

Ignored Input

Bus Grant

Must be asserted/deasserted synchronous to CLKOUT for proper

operation. An external bus arbitration circuit asserts BG when the

DSP56303 becomes the next bus master. When BG is asserted, the

DSP56303 must wait until BB is deasserted before taking bus mastership.

When BG is deasserted, bus mastership is typically given up at the end of

the current bus cycle. This may occur in the middle of an instruction that

requires more than one external bus cycle for execution.

Input/

Output

Ignored Input

Bus Busy

Indicates that the bus is active and must be asserted and deasserted

synchronous to CLKOUT. Only after BB is deasserted can the pending

bus master become the bus master (and then assert the signal again).

The bus master can keep BB asserted after ceasing bus activity,

regardless of whether BR is asserted or deasserted. This is called “bus

parking” and allows the current bus master to reuse the bus without

re-arbitration until another device requires the bus. BB is deasserted by

an “active pull-up” method (that is, BB is driven high and then released

and held high by an external pull-up resistor).

BB requires an external pull-up resistor.

CAS

Output

Tri-stated

Column Address Strobe

When the DSP is the bus master, DRAM uses CAS to strobe the column

address. Otherwise, if the Bus Mastership Enable (BME) bit in the DRAM

Control Register is cleared, the signal is tri-stated.

BCLK

Output

Tri-stated

Bus Clock

When the DSP is the bus master, BCLK is active when the OMR[ATE] is

set. When BCLK is active and synchronized to CLKOUT by the internal

PLL, BCLK precedes CLKOUT by one-fourth of a clock cycle.

BCLK

Output

Tri-stated

Bus Clock Not

When the DSP is the bus master, BCLK is the inverse of the BCLK signal.

Otherwise, the signal is tri-stated.

Table 2-8. External Bus Control Signals (Continued)

Signal

Name

Type

State During Reset,

Stop, or Wait

Signal Description

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