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Configuring Interrupts

DSP56303 User’s Manual, Rev. 2

Freescale Semiconductor

4-15

4.4 Configuring Interrupts

DSP56303 interrupt handling, like that for all DSP56300 family members, is optimized for DSP

applications. Refer to the sections describing interrupts in Chapter 2, Core Architecture

Overview, in the DSP56300 Family Manual. Two registers are programmed to configure the

interrupt characteristics:

Interrupt Priority Register-Core (IPRC). Configure the priority levels for the core DMA

interrupts and the external interrupt lines as well as the interrupt line trigger modes.

Interrupt Priority Register-Peripherals (IPRP). Configure the priority levels for the

interrupts used with the internal peripheral devices

The interrupt table resides in the 256 locations of program memory to which the PCU vector base

address (VBA) register points. These locations store the starting instructions of the interrupt

handler for each specified interrupt. The memory is programmed by the bootstrap program at

start-up.

4.4.1 Interrupt Priority Registers (IPRC and IPRP)

There are two interrupt priority registers in the DSP56303. The IPRC (Figure 4-3) is dedicated to

DSP56300 core interrupt sources, and IPRP (Figure 4-4) is dedicated to DSP56303 peripheral

interrupt sources.

Figure 4-3. Interrupt Priority Register-Core (IPRC) (X:$FFFFFF)

IAL0

IAL1

IAL2

IBL0

IBL1

IBL2

ICL0

ICL1

ICL2

IRQA IPL

IRQA mode

IRQB IPL

IRQB mode

IRQC IPL

IRQC mode

IRQD IPL

D0L0

D0L1

D1L0

D1L1

DMA0 IPL

DMA1 IPL

D2L0

D2L1

D3L0

D3L1

D4L0

D4L1

D5L0

D5L1

DMA2 IPL

DMA3 IPL

DMA4 IPL

DMA5 IPL

IDL2

IDL1 IDL0

IRQD mode

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