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数据搜索系统，热门电子元器件搜索 |
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数据搜索系统，热门电子元器件搜索 |
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DSP56303 数据表(PDF) 271 Page - Freescale Semiconductor, Inc |
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DSP56303 数据表(HTML) 271 Page - Freescale Semiconductor, Inc |
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271 / 292 page  Programming Sheets DSP56303 User’s Manual, Rev. 2 Freescale Semiconductor B-27 Figure B-18. SCI Clock Control Registers (SCCR) Application: Date: Programmer: Sheet 2 of 2 SCI SCI Clock Control Register (SCCR) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CD7 CD5 CD4 CD3 CD2 CD1 CD0 23 *= Reserved, Program as 0 CD6 *0 TCM RCM SCP COD CD11 CD10 CD9 CD8 Clock Divider Bits (CD11–CD0) CD11–CD0 Icyc Rate $000 Icyc/1 $001 Icyc/2 $002 Icyc/3 •• •• •• $FFE Icyc/4095 $FFF Icyc/4096 SCI Clock Prescaler 0 = ÷1 1 = ÷ 8 Clock Out Divider 0 = Divide clock by 16 before feed to SCLK 1 = Feed clock to directly to SCLK TCM RCM TX Clock RX Clock SCLK Pin Mode 0 0 Internal Internal Output Synchronous/Asynchronous 0 1 Internal External Input Asynchronous only 1 0 External Internal Input Asynchronous only 1 1 External External Input Synchronous/Asynchronous Receiver Clock Mode/Source 0 = Internal clock for Receiver 1 = External clock from SCLK Transmitter Clock Mode/Source 0 = Internal clock for Transmitter 1 = External clock from SCLK Address X:$FFFF9B Read/Write Reset = $000000 |
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