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Data Sheet

ADE9178

THEORY OF OPERATION

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Host SPI Protocol CRC

The ADE9178 SPI port uses CRC to verify the integrity of the

data received and sent over the SPI. CRC-16-CCITT algorithm with

initial value 0xFFFF is used for this purpose.

The CRC of the command field (COMMAND_HEADER + DATA) is

calculated and compared against the CRC field of the command. If

there is a CRC mismatch, command is not executed, HOST_ERR

pin is raised, and status code 0xA (for more details, see Table 11) is

returned. By default the CRC check is enabled and can be disabled

by writing CRC_DIS bit of CONFIG0. For that purpose, use the

following command fields:

►

Command Header = 0x0001AE00

►

CRC = 0x26BE

Note that the SPI command frame size is fixed and application

should send 2 dummy bytes as CRC even if CRC check is disabled

for the command. The 16-bit CRC of the response is appended at

the end of every response. There is no option to disable this but

application can ignore the CRC if there is no need to verify the

integrity of the response.

CRC of Configuration Registers

The configuration register CRC feature monitors many register val-

ues. It also optionally includes 15 register sets that are individually

selectable in the CRC_OPTEN register. The result is stored in the

CRC_RSLT register. If any of the monitored registers change value,

the CRC_RSLT changes as well, and the CRC_CHG bit in the

STATUS1 register is set; this can also be configured to generate

an interrupt on IRQ1. For more details, see CRC_OPTEN in the

Configuration Lock

To prevent accidental overwriting of configuration registers, a provi-

sion to lock writing of configuration registers is provided. The user

can write 0x1 to the CONFIG_LOCK register to lock the ability to

write to the configuration registers. When the lock is enabled, all

writes to configuration registers other than CONFIG_LOCK throw

an error. The configuration register write can be unlocked by writing

0x0 to the CONFIG_LOCK register.

Burst Register Read

The ADE9178 supports burst reading of up to 256 registers by us-

ing the NUM_REGISTERS field in the SPI write command header

(for more details, see the Host SPI section). There are five address

ranges supported by the ADE9178, which are shown in Table 12.

Table 12. Burst Read Address Ranges

Name

Address Range (Inclusive)

Config registers

0x0 to 0xDD

Output registers

0x200 to 0x295

Status registers

0x400 to 0x40B

Output registers grouped by function

0x600 to 0x630

Output registers grouped by phase

0x631 to 0x661

For each address space, wrap-around happens if start address and

NUM_REGISTERS combination gives an address greater than last

address in that range. For example, if application issues a read

with 0x290 as ADDRESS and NUM_REGISTERS as 10, then the

returned registers are 0x290, 0x291, 0x292, 0x293, 0x294, 0x295,

0x200, 0x201, 0x202, and 0x203.

There are some address gaps in the register map, which are not

documented and untested. Burst read works as if it is a normal

Clear-on-Read Registers

The energy registers can be configured to be clear-on-read (for

more details, see the Energy Calculation section) and peak regis-

ters are always clear-on-read. If burst access is issued for such

registers, registers are cleared just before initiating the SPI traction

for response. For example, addresses of IPEAK, VPEAK, and

AUXPEAK are 0x285, 0x286, and 0x287, respectively. If a read

is issued with ADDRESS 0x284 and NUM_REGISTERS as 4,

all three peak registers are cleared before sending the values of

registers from 0x284 to 0x287.

Note that the exact time of clearing the register is not defined. It

can vary between the time the command reaches the ADE9178 and

the HOST_RDY pin is asserted. Even if the transaction is aborted

or the response is corrupted for clear-on-register register reads, the

FULL-SCALE CODES AND CONVERSION

EQUATIONS

The ADE9178 calculates various parameters on the input channels

and provides output as 32-bit registers in fixed point format. It

can be easily converted to physical units such as amperes, volts,

and watt. It is required to have knowledge of what is the input

voltage and current that gives full-scale ADC input and what are

the output registers given by the ADE9178 for such input. Signals

corresponding to full-scale input in physical units are referred as

XFS, where, XFS can be either IFS, VFS_T, or AUXFS based on

whether channels are current, voltage, or auxiliary, respectively.

These parameters are choices made during system design and

it is assumed that the application developers are already aware

of it. Table 13 summarizes the ADE9178 register values when

full-scale inputs are provided at ADC inputs. These are referred as

XFS_CODES, where X can vary based on type of the register.

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