ADE9178 datasheet(50/122 Pages) AD

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Data Sheet

ADE9178

THEORY OF OPERATION

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INTERRUPTS AND STATUS OUTPUTS

The ADE9178 provides five 32-bit registers STATUS0, STATUS1,

STATUS2, STATUS3, and ERROR_STATUS to indicate various

events/errors in the system. There are corresponding MASK0,

MASK1, MASK2, MASK3, and ERROR_MASK registers, which can

be used to map a particular event to one of the interrupt pins IRQ0,

IRQ1, IRQ2, or IRQ3. These pins go low when an enabled interrupt

occurs and stays low until the event is acknowledged by writing 1 to

the corresponding bit in the STATUS register.

Note that STATUS0 and STATUS1 contains exactly same events

except the 14th bit. STATUS0 14th bit is for RSTDONE (nonmaska-

ble) and STATUS1 14th bit is for ERROR (bit enabled by default in

the MASK1 register). Two registers are provided to allow mapping

to IRQ0 or IRQ1 for these events.

As there is no dedicated IRQ pin associated with the ERROR_STA-

TUS register, bit 14 of the STATUS1 register (ERROR) is used

to map any error bits in the ERROR_STATUS register to the

IRQ1 pin. If an error occurs the STATUS1 ERROR bit is asserted

only if the corresponding bit is set in the ERROR_MASK register.

STATUS1 bit 14 (ERROR) is masked to IRQ1 by default. Read the

ERROR_STATUS register to determine the cause of the interrupt.

For example, if a user wants to generate an interrupt on

IRQ1 whenever ADC_RUNTIME_ERROR is detected from ER-

ROR_STATUS, set bit 3 in the ERROR_MASK register. Bit 14

of STATUS1 is logical OR of the ERROR_STATUS bits set in

ERROR_MASK.

The ADE91xx ADCs have 3 status registers (ADC_STATUS0,

ADC_STATUS1, and ADC_STATUS2). These status registers are

mapped to a corresponding bit in the ERROR_STATUS register of

the ADE9178. For example, ADC_STATUS0 of ADC0 is mapped

to the ADC0_STATUS0 bit in the ERROR_STATUS register. As

multiple bits in the ADC_STATUSx register are mapped to a single

bit in the ERROR_STATUS register of the ADE9178, select bits in

the ADC_STATUSx register are logic OR. The bits that are logic OR

in each ADC_STATUS register is as follows: ADC_STATUS0[0:5],

ADC_STATUS1[1:3], and ADC_STATUS2[0:6]. For example, if any

bits are set in ADC_STATUS1 register of ADC2, the corresponding

ADC2_STATUS1 bit is set in the ERROR_STATUS register of the

ADE9178.

If a bit is set in the ERROR_STATUS register, the corresponding

ADC_STATUSx register can be read to understand what caused

the error. To clear the errors, write 1 to the corresponding bits in the

ERROR_STATUS register and the ADC_STATUSx register. If the

ADC_STATUSx register is not cleared, the bit in ERROR_STATUS

Figure 69. ADC_STATUSX to ERROR_STATUS Register Mapping

ERROR_STATUS Register Table

Table 27 describes what each bit means in the register, how to

debug during project development and how to handle if the error

appears while in the field.

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