ADE9178 datasheet(43/122 Pages) AD

43 / 122 page

Data Sheet

ADE9178

THEORY OF OPERATION

analog.com

Rev. A | 43 of 122

Figure 59. Filtered RMS Datapath

Table 21. Filtered RMS Settling Time with 50 Hz Input

Filtered RMS Settling Time (Sec)

Configuration

FS = 99%

FS = 99.9%

HPF On, LPF On

0.95654

1.44245

Zero-Crossing Detection

The ADE9178 offers zero-crossing detection on all ADC input

signals. Each channel is associated with a ZX bit in STATUS0 and

STATUS1 registers, which are set when zero crossing is detected

on that channel. However, ZX output from the ADE9178 has very

high jitter and hence is not intended for external use. A user are

expected to use zero-crossing detection output from the ADC if high

accuracy is required.

The ZX_SRC_SEL in the CONFIG0 register select whether data

going into the zero-crossing detection circuit comes before or after

the HPF and phase compensation (for more details, see Figure

49). By default, the xPCF waveforms after the HPF are used

for zero-crossing detection. The zero-crossing circuit is the time

base for line period, angle, RMS half measurements, and energy

accumulation using line-cycle accumulation mode. Note, it is not

recommended to use line-cycle accumulation mode (for more de-

tails, see Table 30).

Note that the HPF has settling times given in Table 16. Thus, for a

fast response, it is recommended to set ZX_SRC_SEL to look for a

zero crossing before the HPF. However, if the HPF is disabled with

HPFDIS = 1 or if ZX_SRC_SEL = 1. Note that a DC offset on the

input may cause the time between negative to positive and positive

to negative zero crossings to change, which indicates that the ZX

detection does not have a 50% duty cycle.

The input signals are passed through a first sequence low pass with

corner frequency of 85 Hz to remove harmonics.

The LPF settling time is 51 samples, 51/4 kSPS, which results

in 12.75 ms. Figure 60 shows the delay between the detected

zero-crossing signal and the input. Note that there is a 3.5 ms to

4.3 ms delay between the input signal zero crossing and the ZX

zero-crossing indication, with a 50 Hz input signal. Zero crossings

are generated on both negative to positive and positive to negative

transitions.

Figure 60. Zero-Crossing Timing

To provide protection from noise for zero-crossing events used

for period calculation, zero-crossing events are not generated for

voltage channels if the absolute value of the ZX LPF filter output

signal is smaller than the threshold ZXTHRSH. Additionally, on all

ADC channels, to prevent false zero crossings after a zero crossing

is generated, 1 ms must elapse before the next zero crossing can

be output. Calculate the zero-crossing threshold, ZXTHRSH, from

the following equation:

ZXTHRSH=PCFFS_CODES×LPFATTENUATION

(31)

where, LPFATTENUATION = 0.86 at 50 Hz and 0.81 at 60 Hz. x is the

fraction of full scale for which the zero crossing is blocked.

For example, for a 50 Hz input, it is required to block zero-crossing

detection for samples 100× lower than full- scale PCF output. Then:

ZXTHRSH=6706531×0.86

100

=57676d (32)

Zero-Crossing Timeout

The zero-crossing timeout feature alerts the user if a zero-crossing

event is not generated after a user- configured amount of time. This

feature is available only on the voltage channels. If a zero crossing

is not detected after (ZXTOUT+1) ms, the corresponding ZXTOx bit

in the STATUS1 register is set. For example, if ZXTOUT is equal to

1000, and if a zero crossing is not detected on phase A for 1001

ms, then ZXTOAV bit is set in the STATUS1 register.

Combined Voltage Zero Crossing

Apart from zero-crossing input signal, the ADE9178 provides zero

crossing of a combined signal from AV. BV, and CV. The com-

bined signal is formed as (AV + BV − CV)/2. This zero crossing,

ZX_COMB, is stable even if one or more phases drops out.

Zero-Crossing Use in Other Functions

The following features are dependent on zero-crossing detection.

The behavior of each feature when zero crossing is absent is given

in Table 22.

ADE9178 数据表(PDF) 43 Page - Analog Devices

ADE9178 数据表(HTML) 43 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载