ADE9178 datasheet(54/122 Pages) AD

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Data Sheet

ADE9178

THEORY OF OPERATION

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IRQ Reoccurrence Behavior

Most bits of STATUS0 and STATUS1 (for example, CFx, RMSO-

NERDY, PF_RDY, and ZXx) are associated with an event and these

bits are set whenever the corresponding events occur. For certain

other bits, the rate at which the bits are set are dependent upon a

user-configurable value as shown in Table 28.

Table 28. Reoccurrence Behavior

STATUS0 Bits

Reoccurrence Behavior

EGY_RDY

After every EGY_TIME + 1 ms or EGY_TIME +

1 half-line cycles. Note, it is recommended to use

time-based accumulation mode (for more details, see

Table 30).

SEQERR

After every SEQ_CYC number of consecutive phase-

sequence errors.

ZXTOAV, ZXTOBV,

ZXTOCV

After every ZXTOUT + 1 ms.

The IRQ reoccurrence behavior for dips/swells bits

in STATUS2/STATUS3 registers depends upon the

DIP_SWELL_x_IRQ_MODE configuration bit in CONFIG0 register.

When this configuration bit is 0 ,then the STATUS register bit is

set only when entering or exiting the dip/swell condition. However,

if the configuration bit is set to 1 then the STATUS bits are set

periodically after every DIP_CYC/SWELL_CYC cycles for as long

as the channel is in dips/swells condition.

POWER MANAGEMENT

Initialising the Chipset

The ADE9178 checks its integrity during boot time. If the check

fails pins HOST_RDY and HOST_ERR go low together and the

ADE9178 enters into a standby mode. A hardware reset is required

to take the ADE9178 out of this state. For more details on how to

perform a hardware reset, see the Hardware Reset section.

Hardware Reset

The ADE9178 has a dedicated reset pin. Hardware reset occurs

when the RESET pin is brought low (default state is weak pull-up)

for at least 1.5 μs (If decoupling capacitors are present, this 1.5 μs

needs to be increased to allow for rise/fall time. With 22 pF and

0.1 μF decoupling, the RESET pin must be brought low for at least

1.5 ms). During a hardware reset, all the registers are set to their

default values. The ADE9178 and ADE91xx reset pins should be

connected together as shown in the Test Circuit section.

If ADE9178 is reset due to power cycle or an unexpected external

interference, RSTDONE bit of STATUS0 register is set and IRQ0 is

raised. The application should follow the full start-up procedure to

configure the ADE9178 into the required state. For more details on

how to configure the ADE9178, see the Quick Start section.

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