ADE9178 datasheet(10/122 Pages) AD

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Data Sheet

ADE9178

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. A | 10 of 122

Figure 4. Pin Configuration

Table 6. Pin Function Descriptions

Pin Number

Mnemonic

Input/Output

Active Low/High

Description

1, 2, 3, 4, 11, 14, 17,

19, 20, 21, 22, 24,

34, 38

N/A1

No Connect.

PULL_UP

N/A1

10 kΩ Pull-Up to VDD.

ADC_MISO

Input

Active High

Data Input for the ADC SPI Port to the supported Analog Front End (AFEs).

ADC_MOSI

Output

Active High

Data Output for the ADC SPI Port from the supported AFEs.

ADC_SCLK

Output

Active High

Serial-Clock Output for the ADC SPI Port.

ADC_CS

Output

Active Low

Chip Select for ADC SPI Port.

ADC_DREADY

Input

Active Low

DREADY Input, Signal to let ADE9178 know that ADC samples are ready. 0.01 µF

capacitor to GND.

12, 13, 15, 16

IRQ0, IRQ1, IRQ2,

IRQ3

Output

Active Low

User-Programmable Interrupt Request Output.

WAVEFORM_TX

Output

Active High

Waveform Streaming through a UART transmit pin.

23, 25

CF1, CF2

Output

Active High

Calibration Frequency (CF) Logic Output. This output provides power information and

is used for operational and calibration purposes.

HOST_MISO

Output

Active High

Data Output for the SPI Port to the Host MCU.

HOST_MOSI

Input

Active High

Data Input for the SPI Port from the Host MCU.

HOST_SCLK

Input

Active High

Serial-Clock Input from the Host MCU.

HOST_CS

Input

Active Low

Chip-Select Input for Host SPI Port.

HOST_RDY

Output

Active Low

Flag to let the Host MCU know that response from the Host Command is ready. 10 kΩ

pull-up to VDD.

HOST_ERR

Output

Active Low

Flag to let the Host MCU know that there is an error during the Command processing.

10 kΩ pull-up to VDD.

DVDDOUT2

N/A1

Bypass with 4.7 nF to GND.

33, 39

PULL_DOWN1,

PULL_DOWN2

N/A1

1 kΩ Pull-Down to GND.

RESET

Input

Active Low

External System Reset Input. The device remains in reset while this pin is in its active

state. When the pin transitions to its inactive state, the device performs a POR reset

(resetting all logic) and begins execution. 22 pF and 0.1 µF to GND.

GND

N/A1

Ground Reference for the Input Circuitry.

VDD

Input

N/A1

Supply Voltage. This pin provides the supply voltage. For specified operation, maintain

the supply voltage at 3.3 V ± 10%. Bypass with 100 nF to GND and 1 μF with 10 mΩ

to 150 mΩ equivalent series resistance (ESR) to GND.

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